CS48560屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由凌云邏輯制造生產(chǎn)的CS48560DSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

Differentiating from the legacy Cirrus multi-standard, multichannel decoders, this new CS485xx family is still based on the same high-performance 32-bit fixed point Digital Signal Processor core but instead is equipped with much less memory, tailoring it for more cost-effective applications associated with multi-channel and virtual-channel sound enhancements.

FEATURES

? Cost-effective, High-performance 32-bit DSP

— 300,000,000 MAC/S (multiply accumulates per second)

— Dual MAC cycles per clock

— 72-bit accumulators are the most accurate in the industry

— 24k x 32 SRAM, 2k blocks - assignable to data or program

— Internal ROM contains a variety of configurable sound enhancement feature sets

— 8-channel internal DMA

— Internal watch-dog DSP lock-up prevention

? DSP Tool Set w/ Private Keys for Protecting Customer IP

? Configurable Serial Audio Inputs/Outputs

— Configurable for all input/output types

— Maximum 32-bit @ 192 kHz

— Supports 32-bit audio sample I/O between DSP chips

— TDM input modes (multiple channels on same line)

— 192 kHz SPDIF transmitter

— Multi-channel DSD direct stream digital SACD input

? Supports Two Different Input Fs Sample Rates

— Output can be master or slave

— Dual processing path capability

— Input supports dual domain slave clocking

— Hardware assist time sampling for sample rate conversion

? Integrated Clock Manager/PLL

— Can operate from external crystal, external oscillator

? Input Fs Auto Detection

? Host & Boot via Serial Interface

? Configurable GPIOs and External Interrupt Input

? 1.8V Core and a 3.3V I/O that is tolerant to 5V input

? Low-power Mode

— “Energy-Star Ready” via low-power mode, 268 μW in standby