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CLVC374AQDWRG4Q1.B中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

CLVC374AQDWRG4Q1.B
廠商型號

CLVC374AQDWRG4Q1.B

功能描述

OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

絲印標(biāo)識

L374AQ1

封裝外殼

SOIC

文件大小

660.88 Kbytes

頁面數(shù)量

16

生產(chǎn)廠商

TI2

中文名稱

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-8 13:48:00

人工找貨

CLVC374AQDWRG4Q1.B價格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

CLVC374AQDWRG4Q1.B規(guī)格書詳情

1FEATURES

· Qualified for Automotive Applications

· ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

· Operates From 2 V to 3.6 V

· Inputs Accept Voltages to 5.5 V

· Max tpd of 8.5 ns at 3.3 V

· Typical VOLP (Output Ground Bounce) < 0.8 V

at VCC = 3.3 V, TA = 25°C

· Typical VOHV (Output VOH Undershoot) > 2 V

at VCC = 3.3 V, TA = 25°C

· Supports Mixed-Mode Signal Operation on All

Ports (5-V Input/Output Voltage With 3.3-V VCC)

· Ioff Supports Partial-Power-Down Mode

Operation

DESCRIPTION/ORDERING INFORMATION

The SN74LVC374A octal edge-triggered D-type flip-flop is designed for 2.7-V to 3.6-V VCC operation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance

loads. This device is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional

bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D)

inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines

without interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in

a mixed 3.3-V/5-V system environment.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

供應(yīng)商 型號 品牌 批號 封裝 庫存 備注 價格
TI/德州儀器
23+
TSSOP-20
9990
只有原裝
詢價
TI
22+
20TSSOP
9000
原廠渠道,現(xiàn)貨配單
詢價
TI/德州儀器
24+
20-TSSO
47186
鄭重承諾只做原裝進(jìn)口現(xiàn)貨
詢價
YAMAHA
23+
QFN
69820
終端可以免費(fèi)供樣,支持BOM配單!
詢價
TI(德州儀器)
24+
TSSOP20
7350
現(xiàn)貨供應(yīng),當(dāng)天可交貨!免費(fèi)送樣,原廠技術(shù)支持!!!
詢價
Texas Instruments
23+
20-TSSOP0.173,4.40mm 寬
7300
專注配單,只做原裝進(jìn)口現(xiàn)貨
詢價
TI/德州儀器
21+
20-TSSO
2990
原裝現(xiàn)貨假一賠十
詢價
TI/德州儀器
25+
原廠封裝
10280
詢價
TI(德州儀器)
24+
TSSOP20
2886
原裝現(xiàn)貨,免費(fèi)供樣,技術(shù)支持,原廠對接
詢價
TI
21+
20-TSSO
12588
原裝正品,自己庫存
詢價