最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

CDCVF857

2.5V 鎖相環(huán)路 DDR 時(shí)鐘驅(qū)動(dòng)器; ? Spread-Spectrum Clock Compatible\n? Operating Frequency: 60 MHz to 220 MHz\n? Low Jitter (Cycle-Cycle): ±35 ps\n? Low Static Phase Offset: ±50 ps\n? Low Jitter (Period): ±30 ps\n? 1-to-10 Differential Clock Distribution (SSTL2)\n? Best in Class for VOX = VDD/2 ±0.1 V\n? Operates From Dual 2.6-V or 2.5-V Supplies\n? Available in a 40-Pin MLF Package, 48-Pin TSSOP Package, 56-Ball MicroStar Junior? BGA Package\n? Consumes FBIN) Are Used to Synchronize the Outputs to the Input Clocks\n? Meets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 Specification\n? Meets/Exceeds Proposed DDRI-400 Specification (JESD82-1A)\n? Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low\n? APPLICATIONS \n? DDR Memory Modules (DDR400/333/266/200)\n? Zero-Delay Fan-Out Buffer\n \n MicroStar Junior is a trademark of Texas Instruments.;

The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able to track spread spectrum clocking for reduced EMI. Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial and industrial temperature ranges.

CDCVF857

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

CDCVF857

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857_16

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857_17

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857DGG

2.5-V PHASE-LOCK LOOP CLOCK DRIVER

CDCVF857DGG

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857DGG

2.5-V PHASE-LOCKED-LOOP CLOCK DRIVER

CDCVF857DGGG4

2.5-V PHASE-LOCK LOOP CLOCK DRIVER