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CDCVF2509A

具有斷電模式的 3.3V 鎖相環(huán)路時(shí)鐘驅(qū)動(dòng)器; ? Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1\n? Spread Spectrum Clock Compatible\n? Operating Frequency 20 MHz to 175 MHz\n? Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps\n? Jitter (cyc - cyc) at 60 MHz to 175 MHz Is Typ = 65 ps\n? Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices\n? Auto Frequency Detection to Disable Device (Power-Down Mode)\n? Available in Plastic 24-Pin TSSOP\n? Phase-Lock Loop Clock Distribution for Synchronous DRAM Applications\n? Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs\n? Separate Output Enable for Each Output Bank\n? External Feedback (FBIN) Terminal Is Used to Synchronize the Outputs to the Clock Input\n? 25- On-Chip Series Damping Resistors\n? No External RC Network Required\n? Operates at 3.3 V\n? APPLICATIONS \n? DRAM Applications\n? PLL Based Clock Distributors\n? Non-PLL Clock Buffer;

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CDCVF2509A operates at a 3.3-V VCC. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state. The device automatically goes into power-down mode when no input signal (< 1 MHz) is applied to CLK; the outputs go into a low state. Unlike many products containing PLLs, the CDCVF2509A does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. For application information, see application reports High Speed Distribution Design Techniques for CDC509/516/2509/2510/2516 (SLMA003) and Using CDC2509A/2510A PLL with Spread Spectrum Clocking (SSC) (SCAA039).The CDCVF2509A is characterized for operation from 0°C to 85°C.Because it is based on PLL circuitry, the CDCVF2509A requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback signals. The PLL can be bypassed by strapping AVCC to ground to use as a simple clock buffer.

CDCVF2509A

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509A

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509A_15

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APW

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APW

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWG4

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWR

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWR

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE

CDCVF2509APWRG4

3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE