CDCU2A877NMKT屬于集成電路（IC）的應用特定時鐘/定時。由美國德州儀器公司制造生產的CDCU2A877NMKT應用特定時鐘/定時專用時鐘和計時 IC（集成電路）產品族中的產品主要用于執(zhí)行與時間或頻率信息生成和分配相關的各種操作，適合的設計環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設備、藍光光盤播放器、以太網(wǎng)設備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

FEATURES

· 1.8-V/1.9-V Phase Lock Loop Clock Driver for

Double Data Rate ( DDR II ) Applications

· Spread Spectrum Clock Compatible

· Operating Frequency: 125 MHz to 410 MHz

· Application Frequency: 160 MHz to 410 MHz

· Low Jitter (Cycle-Cycle): ±40 ps

· Low Output Skew: 35 ps

· Stabilization Time <6 μs

· Distributes One Differential Clock Input to 10

Differential Outputs

· High-Drive Version of CDCUA877

· 52-Ball mBGA (MicroStar Junior? BGA,

0,65-mm pitch)

· External Feedback Pins ( FBIN, FBIN ) are

Used to Synchronize the Outputs to the Input

Clocks

· Meets or Exceeds CUA877/CUA878

Specification PLL Standard for

PC2-3200/4300/5300/6400

· Fail-Safe Inputs

DESCRIPTION

The CDCU2A877 is a high-performance, low-jitter, low-skew, zero-delay buffer that distributes a differential clock

input pair (CK, CK) to 10 differential pairs of clock outputs (Yn, Yn) and to one differential pair of feedback clock

outputs (FBOUT, FBOUT). The clock outputs are controlled by the input clocks (CK, CK), the feedback clocks

(FBIN, FBIN), the LVCMOS control pins (OE, OS), and the analog power input (AVDD). When OE is low, the

clock outputs, except FBOUT/FBOUT, are disabled while the internal PLL continues to maintain its locked-in

frequency. OS (output select) is a program pin that must be tied to GND or VDD. When OS is high, OE functions

as previously described. When OS and OE are both low, OE has no affect on Y7/Y7, they are free running.

When AVDD is grounded, the PLL is turned off and bypassed for test purposes.

When both clock inputs (CK, CK) are logic low, the device enters in a low power mode. An input logic detection

circuit on the differential inputs, independent from input buffers, detects the logic low level and performs in a low

power state where all outputs, the feedback, and the PLL are off. When the clock inputs transition from being

logic low to being differential signals, the PLL turns back on, the inputs and the outputs are enabled, and the

PLL obtains phase lock between the feedback clock pair (FBIN, FBIN) and the clock input pair (CK, CK) within

the specified stabilization time.

The CDCU2A877 is able to track spread spectrum clocking (SSC) for reduced EMI. This device operates from

0°C to 70°C.