CDCS503PW屬于集成電路（IC）的時鐘緩沖器驅(qū)動器。由美國德州儀器公司制造生產(chǎn)的CDCS503PW時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負(fù)載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。

1FEATURES

· Part of a Family of Easy to use Clock

Generator Devices With Optional SSC

· Clock Multiplier With Selectable Output

Frequency and Selectable SSC

· SSC Controllable via 2 External Pins

– ±0%, ±0.5%, ±1%, ±2% Center Spread

· Frequency Multiplication Selectable Between

x1 or x4 With One External Control Pin

· Output Disable via Control Pin

· Single 3.3V Device Power Supply

· Wide Temperature Range –40°C to 85°C

· Low Space Consumption by 8 Pin TSSOP

Package

APPLICATIONS

· Consumer and Industrial Applications

requiring EMI reduction through Spread

Spectrum Clocking and/ or Clock

Multiplication

DESCRIPTION

The CDCS503 is a spread spectrum capable, LVCMOS Input Clock Buffer with selectable frequency

multiplication.

It shares major functionality with the CDCS502 but utilizes a LVCMOS input stage instead of the crystal input

stage of the CDCS502. Also an Output Enable pin has been added to the CDCS503.

The device accepts a 3.3V LVCMOS signal at the input.

The input signal is processed by a PLL, whose output frequency is either equal to the input frequency or

multiplied by the factor of 4.

The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock

frequency with a triangular modulation.

By this, the device can generate output frequencies between 8MHz and 108MHz with or without SSC.

A separate control pin can be used to enable or disable the output. The CDCS503 operates in 3.3V environment.

It is characterized for operation from –40°C to 85°C, and available in an 8-pin TSSOP package.