CDCLVP1204屬于集成電路（IC）的時鐘緩沖器驅(qū)動器。由美國德州儀器公司制造生產(chǎn)的CDCLVP1204時鐘緩沖器，驅(qū)動器時鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負(fù)載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。

1 Features

1? 2:4 Differential Buffer

? Selectable Clock Inputs Through Control Terminal

? Universal Inputs Accept LVPECL, LVDS, and

LVCMOS/LVTTL

? Four LVPECL Outputs

? Maximum Clock Frequency: 2 GHz

? Maximum Core Current Consumption: 45 mA

? Very Low Additive Jitter: <100 fs, RMS in 10-kHz

to 20-MHz Offset Range:

– 57 fs, RMS (typical) at 122.88 MHz

– 48 fs, RMS (typical) at 156.25 MHz

– 30 fs, RMS (typical) at 312.5 MHz

? 2.375-V to 3.6-V Device Power Supply

? Maximum Propagation Delay: 450 ps

? Maximum Output Skew: 15 ps

? LVPECL Reference Voltage, VAC_REF, Available

for Capacitive-Coupled Inputs

? Industrial Temperature Range: –40°C to +85°C

? Supports 105°C PCB Temperature (Measured at

Thermal Pad)

? ESD Protection Exceeds 2 kV (HBM)

2 Applications

? Wireless Communications

? Telecommunications/Networking

? Medical Imaging

? Test and Measurement Equipment

3 Description

The CDCLVP1204 is a highly versatile, low additive

jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL,

LVDS, or LVCMOS inputs for a variety of

communication applications. It has a maximum clock

frequency up to 2 GHz. The CDCLVP1204 features

an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a

control terminal. The overall additive jitter

performance is less than 0.1 ps, RMS from 10 kHz to

20 MHz, and overall output skew is as low as 15 ps,

making the device a perfect choice for use in demanding applications.

The CDCLVP1204 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to four pairs of

differential LVPECL clock outputs (OUT0, OUT3) with

minimum skew for clock distribution. The

CDCLVP1204 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS,

or LVCMOS/LVTTL.

The CDCLVP1204 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in

single-ended mode, the LVPECL bias voltage

(VAC_REF) must be applied to the unused negative

input terminal. However, for high-speed performance

up to 2 GHz, differential mode is strongly

recommended.

The CDCLVP1204 is characterized for operation from

–40°C to +85°C.