CDCLVP110VFG4屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由美國(guó)德州儀器公司制造生產(chǎn)的CDCLVP110VFG4時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

1FEATURES

? Distributes One Differential Clock Input Pair

LVPECL/HSTL to 10 Differential LVPECL Clock

Outputs

? Fully Compatible With LVECL/LVPECL/HSTL

? Single Supply Voltage Required, ±3.3-V or

±2.5-V Supply

? Selectable Clock Input Through CLK_SEL

? Low-Output Skew (Typ 15 ps) for

Clock-Distribution Applications

? VBB Reference Voltage Output for

Single-Ended Clocking

? Available in a 32-Pin LQFP Package

? Frequency Range From DC to 3.5 GHz

? Pin-to-Pin Compatible With MC100 Series

EP111, ES6111, LVEP111, PTN1111

DESCRIPTION

The CDCLVP110 clock driver distributes one

differential clock pair of either LVPECL or HSTL

(selectable) input, (CLK0, CLK1) to ten pairs of

differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The

CDCLVP110 can accept two clock sources into an

input multiplexer. The CLK0 input accepts either

LVECL/LVPECL input signals, while CLK1 accepts an

HSTL input signal when operated under LVPECL

conditions. The CDCLVP110 is specifically designed

for driving 50-Ω transmission lines.

The VBB reference voltage output is used if

single-ended input operation is required. In this case

the VBB pin should be connected to CLK0 and

bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz,

the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from

–40°C to 85°C.