CDC351DBR屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動(dòng)器。由美國德州儀器公司制造生產(chǎn)的CDC351DBR時(shí)鐘緩沖器，驅(qū)動(dòng)器時(shí)鐘緩沖器和驅(qū)動(dòng)器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號(hào)在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號(hào)，以同步系統(tǒng)內(nèi)的活動(dòng)。盡管這些器件最常用到的功能就是緩沖（即，為使信號(hào)不受驅(qū)動(dòng)負(fù)載的影響而從某個(gè)信號(hào)源復(fù)制信號(hào)），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號(hào)路徑、按某個(gè)整數(shù)值分割信號(hào)頻率，或進(jìn)行所用電信號(hào)格式轉(zhuǎn)換。

FEATURES

· Low Output Skew, Low Pulse Skew for

Clock-Distribution and Clock-Generation

Applications

· Operates at 3.3-V VCC

· LVTTL-Compatible Inputs and Outputs

· Supports Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

· Distributes One Clock Input to Ten Outputs

· Distributed VCC and Ground Pins Reduce

Switching Noise

· High-Drive Outputs (?32-mA IOH, 32-mA IOL)

· State-of-the-Art EPIC-IIB? BiCMOS Design

Significantly Reduces Power Dissipation

· Package Options Include Plastic

Small-Outline (DW) and Shrink Small-Outline

(DB) Packages

DESCRIPTION

The CDC351 is a high-performance clock-driver circuit that distributes one input (A) to ten outputs (Y) with minimum

skew for clock distribution. The output-enable (OE) input disables the outputs to a high-impedance state. The

CDC351 operates at nominal 3.3-V VCC.

The propagation delays are adjusted at the factory using the P0 and P1 pins. The factory adjustments ensure that the

part-to-part skew is minimized and is kept within a specified window. Pins P0 and P1 are not intended for customer

use and should be connected to GND.