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CDC318ADL.B

絲印：CDC318A；Package：SSOP；1-LINE TO 18-LINE CLOCK DRIVER WITH 12C CONTROL INTERFACE

High-Speed,Low-Skew1-to-18ClockBuffer forSynchronousDRAM(SDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoFourUnbufferedSDRAM DualInlineMemoryModules(DIMMs) I2CSerialInterfaceProvidesIndividual En

CDC318ADLR

1Lineto10LineClockDriver

CDC318ADLR

1-LINETO18-LINECLOCKDRIVERWITH12CCONTROLINTERFACE

High-Speed,Low-Skew1-to-18ClockBuffer forSynchronousDRAM(SDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoFourUnbufferedSDRAM DualInlineMemoryModules(DIMMs) I2CSerialInterfaceProvidesIndividual En

CDC318ADLR.B

1-LINETO18-LINECLOCKDRIVERWITH12CCONTROLINTERFACE

High-Speed,Low-Skew1-to-18ClockBuffer forSynchronousDRAM(SDRAM)Clock BufferingApplications OutputSkew,tsk(o),LessThan250ps PulseSkew,tsk(p),LessThan500ps SupportsuptoFourUnbufferedSDRAM DualInlineMemoryModules(DIMMs) I2CSerialInterfaceProvidesIndividual En

CDC318DL

1-LINETO18-LINECLOCKDRIVERWITHI2CCONTROLINTERFACE

CDC318DLR

1-LINETO18-LINECLOCKDRIVERWITHI2CCONTROLINTERFACE

CEIA-318

RFEquipmentProtectionHighPower

CP318V

SmallSignalTransistorNPN-HighVoltageTransistorChip

PROCESSDETAILS ProcessEPITAXIALPLANAR DieSize26x26MILS DieThickness7.1MILS±0.6MILS BaseBondingPadArea5.5x5.5MILS EmitterBondingPadArea5.5x5.5MILS TopSideMetalizationAl-Si-17,000? BackSideMetalizationAu-12,000?

D318RW

Single&DualOutput3WSIP,WideInputDC/DCConverters

DB318C

FixedInductorsforSurfaceMounting

InductanceRange:1.0~22μH(DB315C),1.0~22μH(DB318C),3.9~27μH(DB320C)) FEATURES ?Lowprofile(4.0mmMax.square,1.5/1.8/2.0mmMax.height). ?MagneticallyshieldedconstructionandlowDCresistanse. ?IdealforDC-DCconverterchokecoilforportableequipments(DVD,DSC,Cellularphone,