CD74HCT652M屬于集成電路（IC）的緩沖器驅(qū)動器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的CD74HCT652M緩沖器，驅(qū)動器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅(qū)動負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

[ /Title (CD74HC652, CD74HCT652)

/Subject (High-Speed CMOS Logic Octal-Bus

Transceiver/Registers, Three-State)

/Author ()

/Keywords ()

/Creator ()

/DOCINFO pdfmark

[ /PageMode /UseOutlines

/DOCVIEW pdfmark

特性 Features

? CD74HC652, CD74HCT652 . . . . . . . . . . . Non-Inverting

? Independent Registers for A and B Buses

? Three-State Outputs

? Drives 15 LSTTL Loads

? Typical Propagation Delay = 12ns at VCC = 5V,CL = 15pF

? Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

? Wide Operating Temperature Range . . . -55oC to 125oC

? Balanced Propagation Delay and Transition Times

? Significant Power Reduction Compared to LSTTL

Logic ICs

? Alternate Source is Philips

? HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

? HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

描述 Description

The CD74HC652 and CD74HCT652 three-state, octal-bus

transceiver/registers use silicon-gate CMOS technology to

achieve operating speeds similar to LSTTL with the low power

consumption of standard CMOS integrated circuits. The

CD74HC652 and CD74HCT652 have non-inverting outputs.

These devices consists of bus transceiver circuits, D-type flipflops,

and control circuitry arranged for multiplexed

transmission of data directly from the data bus or from the

internal storage registers. Output Enables OEAB and OEBA

are provided to control the transceiver functions. SAB and

SBA control pins are provided to select whether real-time or

stored data is transferred. The circuitry used for select control

will eliminate the typical decoding glitch that occurs in a

multiplexer during the transition between stored and real-time

data. A LOW input level selects real-time data, and a HIGH

selects stored data. The following examples demonstrates the

four fundamentals bus-management functions that can be

performed with the octal-bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the

internal D flip-flops by low-to-high transitions at the appropriate

clock pins (CAB or CBA) regardless of the select of the control

pins. When SAB and SBA are in the real-time transfer mode, it

is also possible to store data without using the D-type flip-flops

by simultaneously enabling OEAB and OEBA. In this

configuration, each output reinforces its input. Thus, when all

other data sources to the two sets of bus lines are at high

impedance, each set of bus lines will remain at its last state.