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CD74HCT273

具有復(fù)位功能的高速 CMOS 邏輯八路 D 型觸發(fā)器; ? Common Clock and Asynchronous Master Reset\n? Positive Edge Triggering\n? Buffered Inputs\n? Fanout (Over Temperature Range) \n? Standard Outputs...10 LSTTL Loads\n? Bus Driver Outputs...15 LSTTL Loads\n \n? Wide Operating Temperature Range...–55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n? 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n? HCT Types \n? 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il 1μA at VOL, VOH\n \n Data sheet acquired from Harris Semiconductor;

The ?HC273 and ?HCT273 high speed octal D-Type flip-flops with a direct clear input are manufactured with silicon-gate CMOS technology. They possess the low power consumption of standard CMOS integrated circuits.\n\n Information at the D inputis transferred to the Q outputs on the positive-going edge of the clock pulse. All eight flip-flops are controlled by a common clock (CP) and a common reset (MR). Resetting is accomplished by a low voltage level independent of the clock. All eight Q outputs are reset to a logic 0.

CD74HCT273

High Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273

High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273E

High Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273E

High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273E

High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273EE4

High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273M

High Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273M

High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset

CD74HCT273M

High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset