CD74HC4518屬于集成電路（IC）的計數(shù)器除法器。由美國德州儀器公司制造生產(chǎn)的CD74HC4518計數(shù)器，除法器計數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進行計數(shù)，然后使用多個并行輸出重新發(fā)送累加的計數(shù)，和/或生成單個輸出信號轉(zhuǎn)換，從而對應用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進行響應。除了簡單的事件計數(shù)，它們還可用于各種頻率合成應用。

Features

? Positive or Negative Edge Triggering

? Synchronous Internal Carry Propagation

? Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

? Wide Operating Temperature Range . . . -55oC to 125oC

? Balanced Propagation Delay and Transition Times

? Significant Power Reduction Compared to LSTTL

Logic ICs

? HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

? HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The CD74HC4518 is a dual BCD up-counter. The ’HC4520

and CD74HCT4520 are dual binary up-counters. Each

device consists of two independent internally synchronous

4-stage counters. The counter stages are D-type flip-flops

having interchangeable CLOCK and ENABLE lines for

incrementing on either the positive-going or the negativegoing

transition of CLOCK. The counters are cleared by high

levels on the MASTER RESET lines. The counter can be

cascaded in the ripple mode by connecting Q3 to the

ENABLE input of the subsequent counter while the CLOCK

input of the latter is held low.