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CD74HC42

High-Speed CMOS Logic BCD-to-Decimal Decoders (1 of 10)

Features ?BufferedInputsandOutputs ?TypicalPropagationDelay:12nsatVCC=5V, CL=15pF,TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?WideOperatingTempera

CD74HC42

高速 CMOS 邏輯 10 選 1 BCD 至十進制解碼器; ? Buffered Inputs and Outputs\n? Typical Propagation Delay: 12ns at VCC = 5V, CL = 15pF, TA = 25°C\n? Fanout (Over Temperature Range) \n - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n? Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n? Wide Operating Temperature Range . . . -55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n - 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n? HCT Types \n - 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il 1μA at VOL, VOH;

The ?HC42 and CD74HCT42 BCD-to-Decimal Decoders utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL decoders with the low power consumption of standard CMOS integrated circuits. These devices have the capability of driving 10 LSTLL loads and are compatible with the standard LS logic family. One of ten outputs (low on select) is selected in accordance with the BCD input. Non-valid BCD inputs result in none of the outputs being selected (all outputs are high).\n\n

CD74HC42

High Speed CMOS Logic BCD To Decimal Decoder 1 of 10

CD74HC42

High-Speed CMOS Logic BCD-to-Decimal Decoders

CD74HC42

High-Speed CMOS Logic BCD-to-Decimal Decoders (1 of 10)

CD74HC423

High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Description TheHarrisCD74HC123,CD74HCT123,CD74HC423andCD74HCT423aredualmonostablemultivibratorswithresets.Theyareallretriggerableanddifferonlyinthatthe123typescanbetriggeredbyanegativetopositiveresetpulse;whereasthe423typesdonothavethisfeature.Anexte

CD74HC423

High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Features ?OverridingResetTerminatesOutputPulse ?TriggeringFromtheLeadingorTrailingEdge ?QandQBufferedOutputs ?SeparateResets ?WideRangeofOutput-PulseWidths ?SchmittTriggeronBothAandBInputs ?Fanout(OverTemperatureRange) -StandardOutputs........

CD74HC423

High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Features ?OverridingResetTerminatesOutputPulse ?TriggeringFromtheLeadingorTrailingEdge ?QandQBufferedOutputs ?SeparateResets ?WideRangeofOutput-PulseWidths ?SchmittTriggeronBothAandBInputs ?Fanout(OverTemperatureRange) -StandardOutputs........

CD74HC423

具有復(fù)位功能的高速 CMOS 邏輯雙路可重觸發(fā)單穩(wěn)態(tài)多諧振蕩器; ? Overriding Reset Terminates Output Pulse\n? Triggering From the Leading or Trailing Edge\n? Q and Q\\ Buffered Outputs\n? Separate Resets\n? Wide Range of Output-Pulse Widths\n? Schmitt Trigger on Both A\\ and B Inputs\n? Fanout (Over Temperature Range) \n? Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n? Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n \n? Wide Operating Temperature Range . . . –55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n? 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n? HCT Types \n? 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il 1μA at VOL, VOH;

The ?HC123, ?HCT123, CD74HC423 and CD74HCT423 are dual monostable multivibrators with resets. They are all retriggerable and differ only in that the 123 types can be triggered by a negative to positive reset pulse; whereas the 423 types do not have this feature. An external resistor (RX) and an external capacitor (CX) control the timing and the accuracy for the circuit. Adjustment of Rx and CX provides a wide range of output pulse widths from the Q and Q\\ terminals. Pulse triggering on the A\\ and B inputs occur at a particular voltage level and is not related to the rise and fall times of the trigger pulses.\n\n Once triggered, the output pulse width may be extended by retriggering inputs A\\ and B. The output pulse can be terminated by a LOW level on the Reset (R) pin. Trailing edge triggering (A)\\ and leading edge triggering (B) inputs are provided for triggering from either edge of the input pulse. If either Mono is not used each input on the unused device (A\\, B, and R\\) must be terminated high or low.\n\nThe minimum value of external resistance, Rx is typically 5k. The minimum value external capacitance, CX, is 0pF. The calculation for the pulse width is tW = 0.45 RXCX at VCC = 5V.

CD74HC423E

High Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets

Description TheHarrisCD74HC123,CD74HCT123,CD74HC423andCD74HCT423aredualmonostablemultivibratorswithresets.Theyareallretriggerableanddifferonlyinthatthe123typescanbetriggeredbyanegativetopositiveresetpulse;whereasthe423typesdonothavethisfeature.Anexte