CD74HC4060PW屬于集成電路（IC）的計數(shù)器除法器。由美國德州儀器公司制造生產(chǎn)的CD74HC4060PW計數(shù)器，除法器計數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對輸入發(fā)生的邏輯轉(zhuǎn)換進行計數(shù)，然后使用多個并行輸出重新發(fā)送累加的計數(shù)，和/或生成單個輸出信號轉(zhuǎn)換，從而對應(yīng)用某些整數(shù)數(shù)量輸入信號轉(zhuǎn)換進行響應(yīng)。除了簡單的事件計數(shù)，它們還可用于各種頻率合成應(yīng)用。

Features

? Onboard Oscillator

? Common Reset

? Negative-Edge Clocking

? Fanout (Over Temperature Range)

- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

? Wide Operating Temperature Range . . . -55oC to 125oC

? Balanced Propagation Delay and Transition Times

? Significant Power Reduction Compared to LSTTL

Logic ICs

? HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

? HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il ≤ 1μA at VOL, VOH

Description

The ’HC4060 and ’HCT4060 each consist of an oscillator

section and 14 ripple-carry binary counter stages. The

oscillator configuration allows design of either RC or crystal

oscillator circuits. A Master Reset input is provided which

resets the counter to the all-0’s state and disables the

oscillator. A high level on the MR line accomplishes the reset

function. All counter stages are master-slave flip-flops. The

state of the counter is advanced one step in binary order on

the negative transition of φI (and φO). All inputs and outputs

are buffered. Schmitt trigger action on the input-pulse-line

permits unlimited rise and fall times.

In order to achieve a symmetrical waveform in the oscillator

section the HCT4060 input pulse switch points are the same

as in the HC4060; only the MR input in the HCT4060 has

TTL switching levels.