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CD74HC393

高速 CMOS 邏輯雙路 4 級二進制計數(shù)器; ? Fully Static Operation\n? Buffered Inputs\n? Common Reset\n? Negative-Edge Clocking\n? Fanout (Over Temperature Range) \n? Standard Outputs . . . 10 LSTTL Loads\n? Bus Driver Outputs . . . 15 LSTTL Loads\n \n? Wide Operating Temperature Range . . . –55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n? 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n? HCT Types \n? 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il 1μA at VOL, VOH\n \n Data sheet acquired from Harris Semiconductor;

The ?HC393 and ?HCT393 are 4-stage ripple-carry binary counters. All counter stages are master-slave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

CD74HC393

High Speed CMOS Logic Dual 4 -Stage Binary Counter

CD74HC393

High-Speed CMOS Logic Dual 4-Stage Binary Counter

CD74HC393

High-Speed CMOS Logic Dual 4-Stage Binary Counter

CD74HC393E

High Speed CMOS Logic Dual 4 -Stage Binary Counter; ? Fully Static Operation\n? Buffered Inputs\n? Common Reset\n? Negative-Edge Clocking\n? Fanout (Over Temperature Range)\n? - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n? - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n? Wide Operating Temperature Range . . . -55oC to 125oC\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types\n? - 2V to 6V Operation\n? - High Noise Immunity: NIL= 30%, NIH= 30% of VCC at VCC= 5V\n? HCT Types\n? - 4.5V to 5.5V Operation\n? - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min)\n? - CMOS Input Compatibility, Il ≤1μA at VOL, VOH;

Description\nThe Harris CD74HC393 and CD74HCT393 are 4-stage ripple-carry binary counters. Al counter stages are master slave flip-flops. The state of the stage advances one count on the negative transition of each clock pulse; a high voltage level on the MR line resets all counters to their zero state. All inputs and outputs are buffered.

CD74HC393E

High-Speed CMOS Logic Dual 4-Stage Binary Counter

CD74HC393E

High-Speed CMOS Logic Dual 4-Stage Binary Counter

CD74HC393E

High-Speed CMOS Logic Dual 4-Stage Binary Counter

CD74HC393E

High Speed CMOS Logic Dual 4 -Stage Binary Counter

CD74HC393E

High Speed CMOS Logic Dual 4 -Stage Binary Counter