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CD74HC109

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC109

具有設(shè)置和復(fù)位端的高速 CMOS 邏輯雙路正邊沿觸發(fā)式 J-K 觸發(fā)器; ? Asynchronous Set and Reset\n? Schmitt Trigger Clock Inputs\n? Typical fMAX = 54MHz at VCC = 5V, CL = 15pF, A = 25°C\n? Fanout (Over Temperature Range) \n? Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n? Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n \n? Wide Operating Temperature Range . . . -55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n? 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n? HCT Types \n? 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il 1μA at VOL, VOH;

The ?HC109 and ?HCT109 are dual J-K\\ flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).\n\n The flip-flop is set and reset by active-low S\\ and R\\, respectively. A low on both the set and reset inputs simultaneously will force both Q and Q\\ outputs high. However, both set and reset going high simultaneously results in an unpredictable output condition.

CD74HC109

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD74HC109

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD74HC109

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD74HC109

Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

CD74HC109E

Marking：CD74HC109E；Package：PDIP；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC109E.A

Marking：CD74HC109E；Package：PDIP；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC109M

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi

CD74HC109M96

Marking：HC109M；Package：SOIC；Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger

Features ?AsynchronousSetandReset ?SchmittTriggerClockInputs ?TypicalfMAX=54MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs...............10LSTTLLoads -BusDriverOutputs.............15LSTTLLoads ?Wi