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CD74HC107

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ?HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes ?AsynchronousReset ?ComplementaryOutputs ?BufferedInputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs.....

CD74HC107

具有復位功能的高速 CMOS 邏輯雙路負邊沿觸發(fā)式 J-K 觸發(fā)器; ? Hysteresis on Clock Inputs for Improved Noise Immunity and Increased Input Rise and Fall Times\n? Asynchronous Reset\n? Complementary Outputs\n? Buffered Inputs\n? Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, TA = 25°C\n? Fanout (Over Temperature Range) \n? Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads\n? Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads\n \n? Wide Operating Temperature Range . . . -55°C to 125°C\n? Balanced Propagation Delay and Transition Times\n? Significant Power Reduction Compared to LSTTL Logic ICs\n? HC Types \n? 2V to 6V Operation\n? High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V\n \n? HCT Types \n? 4.5V to 5.5V Operation\n? Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)\n? CMOS Input Compatibility, Il 1μA at VOL, VOH;

The ?HC107 and ?HCT107 utilize silicon gate CMOS technology to achieve operating speeds equivalent to LSTTL parts. They exhibit the low power consumption of standard CMOS integrated circuits, together with the ability to drive 10 LSTTL loads.\n\n These flip-flops have independent J, K, Reset and Clock inputs and Q and Q\\ outputs. They change state on the negative-going transition of the clock pulse. Reset is accomplished asynchronously by a low level input.\n\n This device is functionally identical to the HC/HCT73 but differs in terminal assignment and in some parametric limits.\n\n The HCT logic family is functionally as well as pin compatible with the standard LS family.

CD74HC107

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

CD74HC107

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

CD74HC107

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

CD74HC107E

Marking：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ?HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes ?AsynchronousReset ?ComplementaryOutputs ?BufferedInputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs.....

CD74HC107E.A

Marking：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ?HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes ?AsynchronousReset ?ComplementaryOutputs ?BufferedInputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs.....

CD74HC107EE4

Marking：CD74HC107E；Package：PDIP；Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ?HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes ?AsynchronousReset ?ComplementaryOutputs ?BufferedInputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs.....

CD74HC107M

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ?HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes ?AsynchronousReset ?ComplementaryOutputs ?BufferedInputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs.....

CD74HC107M96

Dual J-K Flip-Flop with Reset Negative-Edge Trigger

Features ?HysteresisonClockInputsforImprovedNoiseImmunity andIncreasedInputRiseandFallTimes ?AsynchronousReset ?ComplementaryOutputs ?BufferedInputs ?TypicalfMAX=60MHzatVCC=5V,CL=15pF, TA=25oC ?Fanout(OverTemperatureRange) -StandardOutputs.....