CD74FCT244AT屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的CD74FCT244AT緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

BiCMOS Technology With Low Quiescent

Power

Buffered Inputs

Noninverted Outputs

Input/Output Isolation From VCC

Controlled Output Edge Rates

64-mA Output Sink Current

Output Voltage Swing Limited to 3.7 V

SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

description/ordering information

The CD74FCT244 and CD74FCT244AT are octal

buffer/line drivers with 3-state outputs using a

small-geometry BiCMOS technology. The output stages are a combination of bipolar and CMOS transistors that

limit the output high level to two diode drops below VCC. This resultant lowering of output swing (0 V to 3.7 V)

reduces the power-bus ringing [a source of electromagnetic interference (EMI)] and minimizes VCC bounce and

ground bounce and their effects during simultaneous output switching. The output configuration also enhances

switching speed and is capable of sinking 64 mA.

These devices are organized as two 4-bit buffers/line drivers with separate active-low output-enable (OE)

inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs

are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.