CD74ACT297M屬于集成電路（IC）的時鐘發(fā)生器PLL頻率合成器。由美國德州儀器公司制造生產(chǎn)的CD74ACT297M時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅動器、分頻器、倍頻器、多路復用器、合成器、扇出分配器和預分頻器。

Speed of Bipolar FCT, AS, and S, With

Significantly Reduced Power Consumption

Digital Design Avoids Analog

Compensation Errors

Easily Cascadable for Higher-Order Loops

Useful Frequency Range

– DC to 110 MHz Typical (K CLK)

– DC to 70 MHz Typical (I/D CLK)

Dynamically Variable Bandwidth

Very Narrow Bandwidth Attainable

Power-On Reset

Output Capability

– Standard: XORPD OUT, ECPD OUT

– Bus Driver: I/D OUT

SCR Latch-Up-Resistant CMOS Process

and Circuit Design

Balanced Propagation Delays

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015

description/ordering information

The CD74ACT297 provides a simple, cost-effective solution to high-accuracy, digital, phase-locked-loop

applications. This device contains all the necessary circuits, with the exception of the divide-by-N counter, to

build first-order phase-locked loops as shown in Figure 1.

Both exclusive-OR phase detectors (XORPDs) and edge-controlled (ECPD) phase detectors are provided for

maximum flexibility.

Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy

for the designer to incorporate ripple cancellation or to cascade to higher-order phase-locked loops.

The length of the up/down K counter is digitally programmable according to the K-counter function table. With

A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three

stages long, which widens the bandwidth, or capture range, and shortens the lock time of the loop. When A,

B, C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth, or

capture range, and lengthens the lock time. Real-time control of loop bandwidth by manipulating the

A-through-D inputs can maximize the overall performance of the digital phase-locked loop.