CD74AC163E屬于集成電路（IC）的計(jì)數(shù)器除法器。由美國(guó)德州儀器公司制造生產(chǎn)的CD74AC163E計(jì)數(shù)器，除法器計(jì)數(shù)器和除法器 IC 是數(shù)字邏輯器件，可對(duì)輸入發(fā)生的邏輯轉(zhuǎn)換進(jìn)行計(jì)數(shù)，然后使用多個(gè)并行輸出重新發(fā)送累加的計(jì)數(shù)，和/或生成單個(gè)輸出信號(hào)轉(zhuǎn)換，從而對(duì)應(yīng)用某些整數(shù)數(shù)量輸入信號(hào)轉(zhuǎn)換進(jìn)行響應(yīng)。除了簡(jiǎn)單的事件計(jì)數(shù)，它們還可用于各種頻率合成應(yīng)用。

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

description/ordering information

The ’AC163 devices are 4-bit binary counters.

These synchronous, presettable counters feature

an internal carry look-ahead for application in

high-speed counting designs. Synchronous

operation is provided by having all flip-flops

clocked simultaneously so that the outputs

change, coincident with each other, when instructed by the count-enable (ENP, ENT) inputs and internal gating.

This mode of operation eliminates the output counting spikes normally associated with synchronous

(ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge

of the clock waveform.

The counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.

Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes

the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is synchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low

after the next low-to-high transition of CLK, regardless of the levels of the enable inputs. This synchronous clear

allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The

active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000

(LLLL).

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15, with QA high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

These devices feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.