CD74AC112E屬于集成電路（IC）的觸發(fā)器。由美國德州儀器公司制造生產(chǎn)的CD74AC112E觸發(fā)器觸發(fā)器是能夠存儲單個邏輯狀態(tài)或信息“位”的基本數(shù)字存儲器件。這些器件至少有兩個輸入；一個或多個用于傳遞要存儲的數(shù)據(jù)，另一個用于指示存儲該數(shù)據(jù)的時間點。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對提供給其輸入的信號有不同的響應(yīng)，可用于實現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時鐘信號時才會改變。

AC Types Feature 1.5-V to 5.5-V Operation

and Balanced Noise Immunity at 30% of the

Supply Voltage

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

description/ordering information

The ’AC112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset

(PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE

and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to

the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and

is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs

may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle

flip-flops by tying J and K high.