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CD54ACT112

Dual “J-K” Flip-Flop with Set and Reset

Description TheCD54AC112/3AandCD54ACT112/3Aaredual“J-K”flip-flopswithsetandresetthatutilizetheHarrisAdvancedCMOSLogictechnology. TheCD54AC112/3AandCD54ACT112/3Aaresuppliedin16leaddual-in-lineceramicpackages(Fsuffix).

CD54ACT112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

CD54ACT112

具有設(shè)置和復(fù)位端的雙路負(fù)邊沿觸發(fā)式 J-K 觸發(fā)器; ? Inputs Are TTL-Voltage Compatible\n? Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption\n? Balanced Propagation Delays\n? ±24-mA Output Drive Current \n? Fanout to 15 F Devices\n \n? SCR-Latchup-Resistant CMOS Process and Circuit Design\n? Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015;

The ?ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR\\ are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by tying J and K high.

CD54ACT112

Dual “J-K” Flip-Flop with Set and Reset;

CD54ACT112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT112

Dual j-k Flip-Flop with Set and Reset

CD54ACT112F3A

Marking：CD54ACT112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

CD54ACT112F3A.A

Marking：CD54ACT112F3A；Package：CDIP；DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

InputsAreTTL-VoltageCompatible SpeedofBipolarF,AS,andS,With SignificantlyReducedPowerConsumption BalancedPropagationDelays 24-mAOutputDriveCurrent Fanoutto15FDevices SCR-Latchup-ResistantCMOSProcessand CircuitDesign Exceeds2-kVESDProtectionPer MIL-STD-883,Me

CD54ACT112_08

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET

CD54ACT112F3A

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET