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CD4520B

CMOS雙路二進制加法計數(shù)器;

CD4518B是雙十進制同步加法計數(shù)器，CD4520B是雙四位二進制同步加法計數(shù)器，二者均是由兩個相同的、內(nèi)置同步4級計數(shù)器。每級計數(shù)器均由D型觸發(fā)器構(gòu)成。由于具有可互換的CLOCK和ENABLE輸入端口，CD4518B/4520B既可由上升沿觸發(fā)也可由下降沿時觸發(fā)。對于單個操作來說，ENALBE輸入用來維持高電平，并在每個CLOCK正向變化時更新計數(shù)器。計數(shù)器在RESET為高電平時清零。計數(shù)器實現(xiàn)在行波模式下的級連，即一個計數(shù)器Q4連接到后繼計數(shù)器的使能輸入端，并且后繼計數(shù)器的CLOCK輸入端保持低電平。\n\nCD4518B和CD4520B的封裝形式有DIP16和SOP16。

CD4520B

CMOS 雙路二進制加法計數(shù)器; ? Medium-speed operation - ???6-MHz typical clock frequency at 10 V\n? Positive- or negative-edge triggering\n? Synchronous internal carry propagation\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full package-temperature range): \n? 1 V at VDD = 5 V\n? 2 V at VDD = 10 V\n? 2.5 V at VDD = 15 V\n \n? 5-V, 10-V, and 15-V parametric ratings\n? Standardized, symmetrical output characteristics\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n? Applications \n? Multistage synchronous counting\n? Multistage ripple counting\n? Frequency dividers\n \n Data sheet acquired from Harris Semiconductor.;

CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.\n\n The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.\n\n The CD4518B and CD4520B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4520B

CD4000系列 邏輯芯片;

CD4520B

CMOS DUAL UP-COUNTERS

CD4520B

CMOS Dual Up-Counters

CD4520B

Cmos Dual Up-Counters

CD4520BMS

CMOS Dual Up Counters

Description CD4518BMSDualBCDUpCounterandCD4520BMSDualBinaryUpCountereachconsistoftwoidentical,internallysynchronous4-stagecounters.ThecounterstagesareD-typeflip-flopshavinginterchangeableCLOCKandENABLElinesforincrementingoneitherthepositive-goingornegative-g

CD4520BE

CMOS DUAL UP-COUNTERS

CD4520BE

CMOS Dual Up-Counters

CD4520BE

Cmos Dual Up-Counters