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CD4072B

2 通道、4 輸入、3V 至 18V 或門; ? Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Standardized, symmetrical output characteristics\n? Noise margin (full package-temperature range): ?????1 V at VDD = 5 V ?????2 V at VDD = 10 V ??2.5 V at VDD = 15 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n Data sheet acquired from Harris Semiconductor;

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logicOR function and supplement the existing family of CMOS gates.\n\n The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-leadthin shrink small-outline packages (PW and PWR suffixes).

CD4072B

CMOS OR GATES

CD4072B

CMOS OR GATES

CD4072B

CMOS OR Gates

CD4072B-MIL

軍用 2 通道、4 輸入、3V 至 18V 或門; ? Medium-Speed Operation - tPLH, tPHL = 60 ns (typ.) at VDD = 10 V\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Standardized, symmetrical output characteristics\n? Noise margin (full package-temperature range): ?????1 V at VDD = 5 V ?????2 V at VDD = 10 V ??2.5 V at VDD = 15 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n Data sheet acquired from Harris Semiconductor;

CD4071B, CD4072B and CD4075B OR gates provide the system designer with direct implementation of the positive-logicOR function and supplement the existing family of CMOS gates.\n\n The CD4071B, CD4072B, and CD4075B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes) and 14-leadthin shrink small-outline packages (PW and PWR suffixes).

CD4072BMS

CMOS OR Gate

Description CD4071BMS,CD4072BMSandCD4075BMSORgatesprovidethesystemdesignerwithdirectimplementationofthepositive-logicORfunctionandsupplementtheexistingfamilyofCMOSgates. TheCD4071BMS,CD4072BMSandCD4075BMSaresuppliedinthese14leadoutlinepackages: Featu

CD4072BMS

CMOS OR Gate

Features ?High-VoltageTypes(20VRating) ?CD4071BMSQuad2-InputORGate ?CD4072BMSDual4-InputORGate ?CD4075BMSTriple3-InputORGate ?MediumSpeedOperation: -tPHL,tPLH=60ns(typ)at10V ?100TestedforQuiescentCurrentat20V ?MaximumInputCurrentof1?Aat18VOverFu

CD4072BD

CMOS OR GATES

CD4072BE

CMOS OR GATES

CD4072BE

CMOS OR GATES