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CD4044B

具有三態(tài)輸出的 CMOS 四路與非 R/S 鎖存器; ? 3-state outputs with common output ENABLE\n? Separate SET and RESET inputs for each latch\n? NOR and NAND configurations\n? 5-V, 10-V, and 15-V parametric ratings\n? Standardized symmetrical output characteristics\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full package temperature range): \n - 1 V at VDD = 5 V\n? 2 V at VDD = 10 V\n? 2.5 V at VDD = 15 V\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n? Applications \n - Holding register in multi-register system\n? Four bits of independent storage with output ENABLE\n? Strobed register\n? General digital logic\n? CD4043B for positive logic systems\n? CD4044B for negative logic systems\nData sheet acquired from Harris Semiconductor;

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic \"1\" or high on the ENABLE input connects the latch states to the Q outputs. A logic \"0\" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.\n The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n

CD4044B

CMOS QUAD 3-STATE R/S LATCHES

CD4044B

CMOS Quad 3-State R/S Latches

CD4044BCM

Quad 3-STATE NOR R/S Latches . Quad 3-STATE NAND R/S Latches

GeneralDescription TheCD4043BCarequadcross-couple3-STATECMOSNORlatches,andtheCD4044BCarequadcross-couple3-STATECMOSNANDlatches.EachlatchhasaseparateQoutputandindividualSETandRESETinputs.Thereisacommon3-STATEENABLEinputforallfourlatches.Alogic“1”on

CD4044BCM

Quad 3-STATE NOR R/S Latches ?

Features nWidesupplyvoltagerange:3Vto15V nLowpower:100nW(typ.) nHighnoiseimmunity:0.45VDD(typ.) nSeparateSETandRESETinputsforeachlatch nNORandNANDconfiguration n3-STATEoutputwithcommonoutputenable Applications Multiplebusstorage Strobedregister Four

CD4044BCN

Quad 3-STATE NOR R/S Latches . Quad 3-STATE NAND R/S Latches

GeneralDescription TheCD4043BCarequadcross-couple3-STATECMOSNORlatches,andtheCD4044BCarequadcross-couple3-STATECMOSNANDlatches.EachlatchhasaseparateQoutputandindividualSETandRESETinputs.Thereisacommon3-STATEENABLEinputforallfourlatches.Alogic“1”on

CD4044BCN

Quad 3-STATE NOR R/S Latches ?

Features nWidesupplyvoltagerange:3Vto15V nLowpower:100nW(typ.) nHighnoiseimmunity:0.45VDD(typ.) nSeparateSETandRESETinputsforeachlatch nNORandNANDconfiguration n3-STATEoutputwithcommonoutputenable Applications Multiplebusstorage Strobedregister Four

CD4044BCSJ

Quad 3-STATE NOR R/S Latches . Quad 3-STATE NAND R/S Latches

GeneralDescription TheCD4043BCarequadcross-couple3-STATECMOSNORlatches,andtheCD4044BCarequadcross-couple3-STATECMOSNANDlatches.EachlatchhasaseparateQoutputandindividualSETandRESETinputs.Thereisacommon3-STATEENABLEinputforallfourlatches.Alogic“1”on

CD4044BCSJ

Quad 3-STATE NOR R/S Latches ?

Features nWidesupplyvoltagerange:3Vto15V nLowpower:100nW(typ.) nHighnoiseimmunity:0.45VDD(typ.) nSeparateSETandRESETinputsforeachlatch nNORandNANDconfiguration n3-STATEoutputwithcommonoutputenable Applications Multiplebusstorage Strobedregister Four

CD4044B-MIL

具有三態(tài)輸出的 CMOS 四路與非 R/S 鎖存器; ? 3-state outputs with common output ENABLE\n? Separate SET and RESET inputs for each latch\n? NOR and NAND configurations\n? 5-V, 10-V, and 15-V parametric ratings\n? Standardized symmetrical output characteristics\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full package temperature range): \n - 1 V at VDD = 5 V\n? 2 V at VDD = 10 V\n? 2.5 V at VDD = 15 V\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n? Applications \n - Holding register in multi-register system\n? Four bits of independent storage with output ENABLE\n? Strobed register\n? General digital logic\n? CD4043B for positive logic systems\n? CD4044B for negative logic systems\nData sheet acquired from Harris Semiconductor;

CD4043B types are quad cross-coupled 3-state CMOS NOR latches and the CD4044B types are quad cross-coupled 3-state CMOS NAND latches. Each latch has a separate Q output and individual SET and RESET inputs. The Q outputs are controlled by a common ENABLE input. A logic \"1\" or high on the ENABLE input connects the latch states to the Q outputs. A logic \"0\" or low on the ENABLE input disconnects the latch states from the Q outputs, resulting in an open circuit condition on the Q outputs. The open circuit feature allows common busing of the outputs.\n The CD4043B and CD4044B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline package (D, DR, DT, DWR, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n