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CD4030B

CMOS High Voltage Logic

Features HighInputVoltageupto20V Noiseimmunitygreaterthan50% Alloutputsbuffered Drivesx2Low-PowerTTLloadsorx1LSTTLload SymmetricalSink&SourceCurrents Directdrop-inreplacementforobsolete componentsinlongtermprograms.

CD4030B

4 通道、4 輸入、3V 至 18V XOR（異或）門; ? Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF\n? 100% tested for quiescent current at 20 V\n? Standardized, symmetrical output characteristics\n? 5-V, 10-V, and 15-V parametric ratings\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full package-temperature range) = ?????1 V at VDD = 5 V ?????2 V at VDD = 10 V ??2.5 V at VDD = 15 V\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n? Applications: \n? Even and odd-parity generators and checkers\n? Logical comparators\n? Adders/subtractors\n? General logic functions\n \n Data sheet acquired from Harris Semiconductor;

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function.\n\n The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-lineplastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrinksmall-outline packages (PW and PWR suffixes).

CD4030B

CMOS QUAD EXCLUSIVE-OR GATE

CD4030B

CMOS High Voltage Logic

CD4030B

CMOS Quad Exclusive - OR Gate

CD4030B

CMOS High Voltage Logic

CD4030B_V02

CMOS High Voltage Logic

Features HighInputVoltageupto20V Noiseimmunitygreaterthan50% Alloutputsbuffered Drivesx2Low-PowerTTLloadsorx1LSTTLload SymmetricalSink&SourceCurrents Directdrop-inreplacementforobsolete componentsinlongtermprograms.

CD4030B-MIL

軍用 4 通道、4 輸入、3V 至 18V XOR（異或）門; ? Medium-speed operation—tPHL, tPLH = 65 ns (typ.) at VDD = 10 V, CL = 50 pF\n? 100% tested for quiescent current at 20 V\n? Standardized, symmetrical output characteristics\n? 5-V, 10-V, and 15-V parametric ratings\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (over full package-temperature range) = ?????1 V at VDD = 5 V ?????2 V at VDD = 10 V ??2.5 V at VDD = 15 V\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ’B’ Series CMOS Devices\"\n? Applications: \n? Even and odd-parity generators and checkers\n? Logical comparators\n? Adders/subtractors\n? General logic functions\n \n Data sheet acquired from Harris Semiconductor;

CD4030B types consist of four independent Exclusive-OR gates. THe CD4030B provides the system designer with a means for direct implementation of the Exclusive-OR function.\n\n The CD4030B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-lineplastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes), and 14-lead thin shrinksmall-outline packages (PW and PWR suffixes).

CD4030BMS

CMOS Quad Exclusive-OR Gate; ? High Voltage Type (20V Rating) \n? Medium-Speed Operation \n? tPHL, tPLH = 65ns (typ) at VDD = 10V, CL = 50pF \n? 100% Tested for Quiescent Current at 20V \n? Standardized Symmetrical Output Characteristics \n? 5V, 10V and 15V Parametric Ratings \n? Maximum Input Current Of 1μA at 18V Over Full Package-Temperature Range; \n? 100nA at 18V and +25oC \n? Noise Margin (Over Full Package Temperature Range): \n? 1V at VDD = 5V \n? 2V at VDD = 10V \n? 2.5V at VDD = 15V \n? Meets All Requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n;

The CD4030BMS types consist of four independent Exclusive- OR gates. The CD4030BMS provides the system designer with a means for direct implementation of the Exclusive-OR function.\nThe CD4030BMS is supplied in these 14-lead outline packages: Braze Seal DIP H4H Frit Seal DIP H1B Ceramic Flatpack H3W

CD4030BMS

CMOS Quad Exclusive-OR Gate

Description TheCD4030BMStypesconsistoffourindependentExclusive-ORgates.TheCD4030BMSprovidesthesystemdesignerwithameansfordirectimplementationoftheExclusive-ORfunction. Features ?HighVoltageType(20VRating) ?Medium-SpeedOperation ???-tPHL,tPLH=65ns(typ)atV