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CD4023BCS

Buffered Triple 3-Input NAND Gate

GeneralDescription ThesetriplegatesaremonolithiccomplementaryMOS(CMOS)integratedcircuitsconstructedwithN-andP-channelenhancementmodetransistors.TheyhaveequalsourceandsinkcurrentcapabilitiesandconformtostandardBseriesoutputdrive.Thedevicesalsohavebufferedoutp

CD4023B-MIL

CMOS 三路 3 輸入與非門; ? Propagation delay time = 60 ns (typ.) at CL = 50 pF, VDD = 10 V\n? Buffered inputs and outputs\n? Standardized symmetrical output characteristics\n? Maximum input current of 1 μA at 18 V over-full package temperature range; 100 nA at 18 V and 25°C\n? 100% tested for quiescent current at 20 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Noise margin (over full package temperature range: ????1 V at VDD = 5 V ????2 V at VDD = 10 V ????2.5 at VDD = 15 V\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of \"B\" Series CMOS Devices\"\n Quad 2 Input—CD4011B Dual 4 Input—CD4012B Triple 3 Input—CD4023B Data sheet acquired from Harris Semiconductor.;

CD4011B, CD4012B, and CD4023B NAND gates provide the system designer with direct implementation of the NANDfunction and supplement the existing family of CMOS gates. All inputs and outputs are buffered.\n\n The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix),14-lead dual-in-line plastic packages (E suffix), 14-lead small-outline packages (M, MT, M96, and NSR suffixes),and 14-lead thin shrink small-outline packages (PWR suffix). The CD4011B and CD4023B types also are supplied in14-lead thin shrink small-outline packages (PW suffix).

CD4023BMS

CMOS NAND Gate; ? High-Voltage Types (20V Rating) \n? Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V \n? Buffered Inputs and Outputs \n? Standardized Symmetrical Output Characteristics \n? Maximum Input Current of 1μA at 18V Over Full Package- Temperature Range; 100nA at 18V and +25oC \n? 100% Tested for Maximum Quiescent Current at 20V \n? 5V, 10V and 15V Parametric Ratings \n? Noise Margin (Over Full Package Temperature Range): \n? 1V at VDD = 5V \n? 2V at VDD = 10V \n? 2.5V at VDD = 15V \n? Meets All Requirements of JEDEC Tentative Standards No. 13B, \"Standard Specifications for Description of \"B\" Series CMOS Device's\n;

CD4011BMS - Quad 2 Input CD4012BMS - Dual 4 Input CD4023BMS - Triple 3 Input\nCD4011BMS, CD4012BMS, and CD4023BMS NAND gates provide the system designer with direct implementation of the NAND function and supplement the existing family of CMOS gates. All inputs and outputs are buffered.\nThe CD4011BMS, CD4012BMS and the CD4023BMS is supplied in these 14 lead outline packages: CD4011B CD4012B CD4023B Braze Seal DIP H4Q H4H H4Q Frit Seal DIP H1B H1B H1B Ceramic Flatpack H3W H3W H3W

CD4023BMS

CMOS NAND Gates

Description CD4011BMS,CD4012BMS,andCD4023BMSNANDgatesprovidethesystemdesignerwithdirectimplementationoftheNANDfunctionandsupplementtheexistingfamilyofCMOSgates.Allinputsandoutputsarebuffered. CD4011BMS-Quad2Input CD4012BMS-Dual4Input CD4023BMS-Triple3I

CD4023BMS

CMOS NAND Gates

Features ?High-VoltageTypes(20VRating) ?PropagationDelayTime=60ns(typ.)atCL=50pF, VDD=10V ?BufferedInputsandOutputs ?StandardizedSymmetricalOutputCharacteristics ?MaximumInputCurrentof1?Aat18VOverFullPackageTemperatureRange;100nAat18Vand+25oC ?100Te

CD4023BC

Buffered Triple 3-Input NAND,NOR Gate

CD4023BCJ

Buffered Triple 3-Input NAND,NOR Gate

CD4023BCN

Buffered Triple 3-Input NAND,NOR Gate

CD4023BE

CMOS NAND GATES

CD4023BE

The CD4011B, CD4012B, and CD4023B types are supplied in 14-lead hermetic dual-in-line ceramic packages