最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

CD4021

8-Stage Static Shift Register

GeneralDescription TheCD4021BCisan8-stageparallelinput/serialoutputshiftregister.Aparallel/serialcontrolinputenablesindividualJAMinputstoeachof8stages.Qoutputsareavailablefromthesixth,seventh,andeighthstages.Alloutputshaveequalsourceandsinkcurrentcapa

CD4021

CMOS 8-Stage Static Shift Registers

Description CD4014BMS-SynchronousParallelorSerialInput/SerialOutput CD4021BMS-AsynchronousParallelInputorSynchronous SerialInput/SerialOutput CD4014BMSandCD4021BMSseriestypesare8-stageparallel-orserial-input/serialoutputregistershavingcommonCLOCK andPARALLEL/SERIAL

CD4021

8-Stage Static Shift Register

GeneralDescription TheCD4021BCisan8-stageparallelinput/serialoutput shiftregister.Aparallel/serialcontrolinputenablesindividual JAMinputstoeachof8stages.Qoutputsareavailable fromthesixth,seventh,andeighthstages.Alloutputshave equalsourceandsinkcurrentcap

CD4021

8-Stage Static Shift Register; ■Wide supply voltage range: 3.0V to 15V\n■High noise immunity: 0.45 VDD(typ.)\n■Low power TTL compatibility:\n??? Fan out of 2 driving 74L or 1 driving 74LS\n■5V–10V–15V parametric ratings\n■Symmetrical output characteristics\n■Maximum input leakage 1 μA at 15V over full temperature range;

General Description\nThe CD4021BC is an 8-stage parallel input/serial output shift register. A parallel/serial control input enables individ ual JAM inputs to each of 8 stages. Q outputs are available from the sixth, seventh, and eighth stages. All outputs have equal source and sink current capabilities and conform to\nstandard “B” series output drive. When the parallel/serial control input is in the logical “0”\nstate, data is serially shifted into the register synchronously with the positive transition of the clock. When the parallel/serial control is in the logical “1” state, data is jammed into each stage of the register asynchronously with the clock.\nAll inputs are protected against static discharge with diodes to VDDand VSS.\n

CD4021BC

8-Stage Static Shift Register

GeneralDescription TheCD4021BCisan8-stageparallelinput/serialoutputshiftregister.Aparallel/serialcontrolinputenablesindividualJAMinputstoeachof8stages.Qoutputsareavailablefromthesixth,seventh,andeighthstages.Alloutputshaveequalsourceandsinkcurrentcapa

CD4021BCM

8-Stage Static Shift Register

GeneralDescription TheCD4021BCisan8-stageparallelinput/serialoutputshiftregister.Aparallel/serialcontrolinputenablesindividualJAMinputstoeachof8stages.Qoutputsareavailablefromthesixth,seventh,andeighthstages.Alloutputshaveequalsourceandsinkcurrentcapa

CD4021BCN

8-Stage Static Shift Register

GeneralDescription TheCD4021BCisan8-stageparallelinput/serialoutputshiftregister.Aparallel/serialcontrolinputenablesindividualJAMinputstoeachof8stages.Qoutputsareavailablefromthesixth,seventh,andeighthstages.Alloutputshaveequalsourceandsinkcurrentcapa

CD4021B-MIL

CMOS 8 級(jí)靜態(tài)移位寄存器; ? Medium speed operation?12 MHz (typ.) clock rate at VDD ? VSS = 10 V\n? Fully static operation\n? 8 master-slave flip-flops plus output buffering and control gating\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (full package-temperature range) = ????????1 V at VDD = 5 V ????????2 V at VDD = 10 V ?????2.5 V at VDD = 15 V\n? Standardized, symmetrical output characteristics\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ?B? Series CMOS Devices\"\n? Applications: \n - Parallel input/serial output data queueing\n? Parallel to serial data conversion\n? General-purpose register\nData sheet acquired from Harris Semiconductor;

CD4014B and CD4021B series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel \"JAM\" inputs to each register stage. Each register stage is D-type, master-slave flip-flop. In addition to an output form stage 8, \"Q\" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014B. In the CD4021B serial entry is synchronous with the clock by parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/SERIAL CONTROL input is high, data is jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021B, the CLOCK input of the internal stage is \"forced\" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.\n The CD4014B and CD4021B series types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix),16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes),and 16-lead thin shrink small-oultine packages (PW and PWR suffixes).\n \n

CD4021BMS

CMOS 8-Stage Static Shift Register; ? High Voltage Types (20V Rating) \n? Medium Speed Operation 12MHz (Typ.) Clock Rate at VDD-VSS = 10V \n? Fully Static Operation \n? 8 Master-Slave Flip-Flops Plus Output Buffering and Control Gating \n? 100% Tested for Quiescent Current at 20V \n? Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC \n? Noise Margin (Full Package Temperature Range) \n? 1V at VDD = 5V \n? 2V at VDD = 10V \n? 2.5V at VDD = 15V \n? Standardized Symmetrical Output Characteristics \n? 5V, 10V and 15V Parametric Ratings \n? Meets All Requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of `B' Series CMOS Devices\n;

CD4014BMS -Synchronous Parallel or Serial Input/Serial Output\nCD4021BMS -Asynchronous Parallel Input or Synchronous Serial Input/Serial Output\nCD4014BMS and CD4021BMS series types are 8-stage parallel- or serial-input/serial output registers having common CLOCK and PARALLEL/SERIAL CONTROL inputs, a single SERIAL data input, and individual parallel \"JAM\" inputs to each register stage. Each register stage is a D-type, master-slave flip-flop. In addition to an output from stage 8, \"Q\" outputs are also available from stages 6 and 7. Parallel as well as serial entry is made into the register synchronously with the positive clock line transition in the CD4014BMS. In the CD4021BMS serial entry is synchronous with the clock but parallel entry is asynchronous. In both types, entry is controlled by the PARALLEL/SERIAL CONTROL input. When the PARALLEL/SERIAL CONTROL input is low, data is serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the PARALLEL/ SERIAL CONTROL input is high, data is jammed into the 8- stage register via the parallel input lines and synchronous with the positive transition of the clock line. In the CD4021BMS, the CLOCK input of the internal stage is \"forced\" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted.\nThe CD4014BMS and CD4021BMS are supplied in these 16 lead outline packages:\nBraze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W

CD4021BMS

CMOS 8-Stage Static Shift Registers

Description CD4014BMS-SynchronousParallelorSerialInput/SerialOutput CD4021BMS-AsynchronousParallelInputorSynchronous SerialInput/SerialOutput CD4014BMSandCD4021BMSseriestypesare8-stageparallel-orserial-input/serialoutputregistershavingcommonCLOCK andPARALLEL/SERIAL