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CD4019B

CMOS 四路與/或選擇門; ? Medium speed operation??tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V\n? Standardized, symmetrical output characteristics\n? 100% tested for quiescent current at 20 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ?B? Series CMOS Devices\"\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (full package-temperature range) = ????????1 V at VDD = 5 V ????????2 V at VDD = 10 V ?????2.5 V at VDD = 15 V\n? Applications: \n - AND-OR select gating\n? Shift-right/shift-left registers\n? True/complement selection\n? AND/OR/Exclusive-OR selection;

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.\n The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix),16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes),and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n

CD4019B

CMOS Quad AND/OR Select Gate

CD4019B

CMOS Quad AND/OR Gate

CD4019BC

Quad AND-OR Select Gate

GeneralDescription TheCD4019BCisacomplementaryMOSquadAND-ORselectgate.LowpowerandhighnoisemarginoverawidevoltagerangeispossiblethroughimplementationofN-andP-channelenhancementmodetransistors.ThesecomplementaryMOS(CMOS)transistorsprovidethebuildingblocks

CD4019BCM

Quad AND-OR Select Gate

GeneralDescription TheCD4019BCisacomplementaryMOSquadAND-ORselectgate.LowpowerandhighnoisemarginoverawidevoltagerangeispossiblethroughimplementationofN-andP-channelenhancementmodetransistors.ThesecomplementaryMOS(CMOS)transistorsprovidethebuildingblocks

CD4019BCN

Quad AND-OR Select Gate

GeneralDescription TheCD4019BCisacomplementaryMOSquadAND-ORselectgate.LowpowerandhighnoisemarginoverawidevoltagerangeispossiblethroughimplementationofN-andP-channelenhancementmodetransistors.ThesecomplementaryMOS(CMOS)transistorsprovidethebuildingblocks

CD4019BCSJ

Quad AND-OR Select Gate

GeneralDescription TheCD4019BCisacomplementaryMOSquadAND-ORselectgate.LowpowerandhighnoisemarginoverawidevoltagerangeispossiblethroughimplementationofN-andP-channelenhancementmodetransistors.ThesecomplementaryMOS(CMOS)transistorsprovidethebuildingblocks

CD4019B-MIL

CMOS 四路與/或選擇門; ? Medium speed operation??tPHL = tPLH = 60 ns (typ.) at CL = 50 pF, VDD = 10 V\n? Standardized, symmetrical output characteristics\n? 100% tested for quiescent current at 20 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of ?B? Series CMOS Devices\"\n? Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (full package-temperature range) = ????????1 V at VDD = 5 V ????????2 V at VDD = 10 V ?????2.5 V at VDD = 15 V\n? Applications: \n - AND-OR select gating\n? Shift-right/shift-left registers\n? True/complement selection\n? AND/OR/Exclusive-OR selection;

CD4019B types consist of four AND/OR select gate configurations, each consisting of two 2-input AND gates driving a single-input OR gate. Selection is accomplished by control bits Ka and Kb. In addition to selection of either channel A or channel B information, the control bits can be applied simultaneously to accomplish the logical A + B function.\n The CD4019B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix),16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes),and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n

CD4019BMS

CMOS Quad AND/OR Select Gate

Description CD4019BMStypesconsistoffourAND/ORselectgateconfigurations,eachconsistingoftwo2-inputANDgatesdrivingasingle2-inputORgate.SelectionisaccomplishedbycontrolbitsKaandKb.InadditiontoselectionofeitherchannelAorchannelBinformation,thecontrolbitsca

CD4019B_15

CMOS Quad AND/OR Gate