最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

CD40160B

具有異步清零功能的 CMOS 同步可編程 4 位十進制計數(shù)器; ·Internal look-ahead for fast counting\n ·Carry output for cascading\n ·Synchronously programmable\n ·Clear asynchronous input (CD40160B, CD40161B)\n ·Clear synchronous input (CD40162B, CD40163B)\n ·Synchronous load control input\n ·Low-power TTL compatibility\n ·Standardized, symmetrical output characteristics\n ·100% tested for quiescent current at 20 V\n ·Maximum input current of 1 μA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n ·Noise margin (full package temperature range): ·1 V at VDD = 5 V\n ·2 V at VDD = 10 V\n ·2.5 V at VDD = 15 V\n\n ·5-V, 10-V, and 15-V parametric ratings\n ·Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n ·Applications ·Programmable binary and decade counting\n ·Counter control/timers\n ·Frequency dividing\n\nData sheet acquired from Harris Semiconductor CD40160B - Decade with Asynchronous Clear CD40161B - Binary with Asynchronous Clear CD40162B - Decade with Synchronous Clear CD40163B - Binary with Synchronous Clear CD40160B, CD40162B, and CD40163B were not acquired from Harris Semiconductor.;

CD40160B, CD40161B, CD40162B, and CD40163B are 4-bit synchronous programmable counters. The CLEAR function of the CD40162B and CD40163B is synchronous and a low level at the CLEAR\\ input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD40160B and CD40161B is asynchronous and a low level at the CLEAR\\ input sets all four outputs low regardless of the state of the CLOCK, LOAD\\, or ENABLE inputs. A low level at the LOAD\\ input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs.\n The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output (COUT). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low.\n The CD40160B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix). The CD40161B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\nThe CD40160B through CD40163B types are functionally equivalent to and pin-compatible with the TTL counter series 74LS160 through 74LS163 respectively.\n \n

CD40160B

Decade Counter with Asynchronous Clear

CD40160B

CMOS Synchronous Programmable 4-Bit Counters

CD40160B

CMOS Synchronous Programmable 4-Bit Counters

CD40160BMS

CMOS Synchronous Programmable 4-Bit Counters; ? High-Voltage Types (20V Rating)\n? CD40160BMS Decade with Asynchronous Clear\n? CD40161BMS Binary with Asynchronous Clear\n? CD40162BMS Decade with Synchronous Clear\n? CD40163BMS Binary with Synchronous Clear\n? Internal Look-Ahead for Fast Counting\n? Carry Output for Cascading\n? Synchronously Programmable\n? Clear Asynchronous Input (CD40160BMS, CD40161BMS)\n? Clear Synchronous Input (CD40162BMS, CD40163BMS)\n? Synchronous Load Control Input\n? Low Power TTL Compatibility\n? Standardized Symmetrical Output Characteristics\n? 100% Tested for Quiescent Current at 20V\n? Maximum Input Current of 1μA at 18V Over Full Package\n?? Temperature Range; 100nA at 18V and +25oC\n? Noise Margin (Over Full Package Temperature Range):\n- 1V at VDD = 5V\n- 2V at VDD = 10V\n- 2.5V at VDD = 15V\n? 5V, 10V and 15V Parametric Ratings\n? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”\n\nApplications\n? Programmable Binary and Decade Counting\n? Counter Control/Timers\n? Frequency Dividing;

CMOS Synchronous Programmable 4-Bit CountersCD40160BMS, CD40161BMS, CD40162BMS and CD40163BMS are 4-bit synchronous programmable counters. The CLEAR function of the CD40162BMS and CD40163BMS is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the CD40160BMS and CD40161BMS is asychronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK,LOAD, or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree\nwith the setup data after the next CLOCK pulse regardless of the conditions of the ENABLE inputs.

CD40160BMS

CMOS Synchronous Programmable 4-Bit Counters

CMOSSynchronousProgrammable4-BitCounters CD40160BMS,CD40161BMS,CD40162BMSandCD40163BMSare4-bitsynchronousprogrammablecounters.TheCLEARfunctionoftheCD40162BMSandCD40163BMSissynchronousandalowlevelattheCLEARinputsetsallfouroutputslowonthenextpositiveCLOCK

CD40160B_15

CMOS Synchronous Programmable 4-Bit Counters

CD40160BC

Decade Counter with Asynchronous Clear

CD40160BCJ

Decade Counter with Asynchronous Clear

CD40160BCN

Decade Counter with Asynchronous Clear