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CD4015

Dual 4-Bit Static Shift Register

GeneralDescription TheCD4015BCcontainstwoidentical,4-stage,serialinput/parallel-outputregisterswithindependent“Data”,“Clock,”and“Reset”inputs.Thelogiclevelpresentattheinputofeachstageistransferredtotheoutputofthatstageateachpositive-goingclocktransition.A

CD4015

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Intersil’sSatelliteApplicationsFlow?(SAF)devicesarefullytestedandguaranteedto100kRADtotaldose.TheseQMLClassTdevicesareprocessedtoastandardflowintendedtomeetthecostandshorterlead-timeneedsoflargevolumesatellitemanufacturers,whilemaintainingahighlevelofr

CD4015

CMOS Dual 4-Stage Static Shift Register With Serial Input/Parallel Output

Description CD4015BMSconsistsoftwoidentical,independent,4-stageserial-input/paralleloutputregisters.EachregisterhasindependentCLOCKandRESETinputsaswellasasingleserialDATAinput.“Q”outputsareavailablefromeachofthefourstagesonbothregisters.Allregisterstages

CD4015

Dual 4-Bit Static Shift Register

CD4015

SEMICONDUCTORS

CD4015B

CMOS Dual 4-Stage Static Shift Register

Features: &Mediumspeedoperation............. 12MHz(typ.)clockrateatVpp—Vg=10V ?Fullystaticoperation 8master-slaveflip-flopsplusinputandoutputbuffering #100%testedforquiescentcurrentat20V #5.V,10-V,and15-Vparametricratings =Standardized,symmetrical

CD4015B

CMOS Dual 4-Stage Static Shift Register

Features: ?Mediumspeedoperation............. 12MHz(typ.)clockrateatVpp—Vgg=10V ?Fullystaticoperation ?8master-slaveflip-flopsplusinputandoutputbuffering ?100%testedforquiescentcurrentat20V ?5.V,10-V,and15-Vparametricratings ?Standardized,symmetr

CD4015BC

Dual 4-Bit Static Shift Register

GeneralDescription TheCD4015BCcontainstwoidentical,4-stage,serialinput/parallel-outputregisterswithindependent“Data”,“Clock,”and“Reset”inputs.Thelogiclevelpresentattheinputofeachstageistransferredtotheoutputofthatstageateachpositive-goingclocktransition.A

CD4015BCM

Dual 4-Bit Static Shift Register

GeneralDescription TheCD4015BCcontainstwoidentical,4-stage,serialinput/parallel-outputregisterswithindependent“Data”,“Clock,”and“Reset”inputs.Thelogiclevelpresentattheinputofeachstageistransferredtotheoutputofthatstageateachpositive-goingclocktransition.A

CD4015BCN

Dual 4-Bit Static Shift Register

GeneralDescription TheCD4015BCcontainstwoidentical,4-stage,serialinput/parallel-outputregisterswithindependent“Data”,“Clock,”and“Reset”inputs.Thelogiclevelpresentattheinputofeachstageistransferredtotheoutputofthatstageateachpositive-goingclocktransition.A