描述 Description

CD4011UB quad 2-input NAND gate provides the system designer with direct implementation of the NAND function andsupplements the existing family of CMOS gates.

The CD4011UB types are supplied in 14-lead hermetic dual-in-line ceramic packages (F3A suffix), 14-lead dual-in-lineplastic packages (E suffix), 14-lead small-outline package (M, MT, M96, NSR suffixes), and 14-lead thin shrink small-outlinepackages (PW and PWR suffixes).

特性 Features

? Propagation delay time = 30 ns (typ). at CL = 50 pF, VDD = 10 V
? Standardized symmetrical output characteristics
? 100% tested for quiescent current at 20V
? Maximum input current of 1 μA at 18 V over full package temperature range; 100nA at 18 V and 25°C
? 5-V, 10-V, and 15-V parametric ratings
? Meets all requirements of JEDEC Tentative Standard No. 13B \"Standard Specifications for Description of ’B’ Series CMOS Devices\"
Data sheet acquired from Harris Semiconductor