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CD40109B

CMOS 四路低向高電壓位轉(zhuǎn)換器（20V 額定電壓）; ? Independence of power supply sequence considerations - VCC can exceed VDD, input signals can exceed both VCC and VDD\n? Up and down level-shifting capability\n? Three-state outputs with separate enable controls\n? Standardized, symmetrical output characteristics\n? 100% tested for quiescent current at 20 V\n? Maximum input current of 1 uA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C\n? Noise margin (full package-temperature range): ???= 1 V at VCC = 5 V, VDD = 10 V ???= 2 V at VCC = 10 V, VDD = 15 V\n? 5-V, 10-V, and 15-V parametric ratings\n? Meets all requirements of JEDEC Tentative Standard No. 13B, \"Standard Specifications for Description of 'B' Series CMOS Devices\"\n? Applications: \n - High-or-low level-shifting with three-state outputs for unidirectional or bidirectional bussing.\n? Isolation of logic subsystems using separate power supplies from supply sequencing, supply loss and supply regulation considerations\nData sheet acquired from Harris Semiconductor;

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.\n The CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals.There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition,with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC;VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter.\nThe CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.\n The CD40109B-Series types are supplied in 16-lead ceramic dual-in-line packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (NSR suffix), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).\n \n

CD40109B

CMOS QUAD LOW-TO-HIGH VOLTAGE LEVEA SHIFTER

CD40109B

CMOS Quad Low-to-High Voltage Lever Shifter

CD40109BMS

CMOS Quad Low-to-High Voltage Level Shifter

Description CD40109BMScontainsfourlow-to-highvoltagelevelshiftingcircuits.Eachcircuitwillshiftalowvoltagedigitallogicinputsignal(A,B,C,D)withlogical1=VCCandlogical0=VSStoahighervoltageoutputsignal(E,F,G,H)withlogical1=VDDandlogical0=VSS. Th

CD40109BMS

CMOS Quad Low-to-High Voltage Level Shifter; ? High Voltage Type (20V Rating)\n? Independence of Power Supply Sequence Considerations\n?? - VCC can Exceed VDD\n?? - Input Signals can Exceed Both VCC and VDD\n? Up and Down Level Shifting Capability\n? Three-State Outputs with Separate Enable Controls\n? 100% Tested for Quiescent Current at 20V\n? 5V, 10V and 15V Parametric Ratings\n? Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC\n? Noise Margin (Over Full Package/Temperature Range)\n?? - 1V at VCC = 5V, VDD = 10V\n?? - 2V at VCC = 10V, VDD = 15V\n? Standardized Symmetrical Output Characteristics\n? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”Applications\n? High or Low Level Shifting with Three-State Outputs for Unidirectional or Bidirectional Bussing\n? Isolation of Logic Subsystems Using Separate Power Supplies from Supply Sequencing, Supply Loss and Supply Regulation Considerations?;

Description\nCD40109BMS contains four low-to-high voltage level shifting circuits. Each circuit will shift a low voltage digital logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a higher voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.\nThe CD40109BMS, unlike other low-to-high level shifting circuits, does not require the presence of the high voltage supply (VDD) before the application of either the low voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC VDD, the CD40109BMS will operate as a high-to-low level shifter.

CD40109B-Q1

汽車(chē)類(lèi) CMOS 四路低向高電壓位轉(zhuǎn)換器（20V 額定電壓）; ? Qualified for Automotive Applications\n? Independent of Power Supply Sequence Considerations \n - VCC Can Exceed VDD\n? Input Signals can Exceed Both VCC and VDD\n? Up and Down Level-Shifting Capability\n? Three-State Outputs With Separate Enable Controls\n? Standardized Symmetrical Output Characteristics\n? 100% Tested for Quiescent Current at 20?V\n? Maximum Input Current: \n - 1 μA at 18 V Over Full Package-Temperature Range\n? 100 nA at 18 V and 25°C\n? Noise Margin (Full Package-Temperature Range): \n - 1 V at VCC = 5 V, VDD = 10 V\n? 2 V at VCC = 10 V, VDD = 15 V\n? 5-V, 10-V, and 15-V Parametric Ratings\n? Meets All Requirements of JEDEC Tentative Standard No. 13B, \"Standard specifications for Description of ?B? Series CMOS Devices\"\n? Latch-Up Performance Meets 50 mA per JESD 78, Class I\n? APPLICATIONS\n - High-or-Low Level-Shifting With Three-State Outputs for Unidirectional or Bidirectional Bussing\n? Isolation of Logic Subsystem Using Separate Power Supplies from Supply Sequencing, Supply Loss, and Supply Regulation Considerations;

CD40109B contains four low-to-high-voltage level-shifting circuits. Each circuit will shift a low-voltage digital-logic input signal (A, B, C, D) with logical 1 = VCC and logical 0 = VSS to a high-voltage output signal (E, F, G, H) with logical 1 = VDD and logical 0 = VSS.\n The RCA-CD40109, unlike other low-to-high level-shifting circuits, does not require the presence of the high-voltage supply (VDD) before the application of either the low-voltage supply (VCC) or the input signals. There are no restrictions on the sequence of application of VDD, VCC, or the input signals. In addition, with one exception there are no restrictions on the relative magnitudes of the supply voltages or input signals within the device maximum ratings, provided that the input signal swings between VSS and at least 0.7 VCC; VCC may exceed VDD, and input signals may exceed VCC and VDD. When operated in the mode VCC > VDD, the CD40109 will operate as a high-to-low level-shifter. \nThe CD40109 also features individual three-state output capability. A low level on any of the separately enabled three-state output controls produces a high-impedance state in the corresponding output.\n \n

CD40109B_15

CMOS Quad Low-to-High Voltage Lever Shifter

CD40109BE

CMOS QUAD LOW-TO-HIGH VOLTAGE LEVEA SHIFTER

CD40109BE

CMOS Quad Low-to-high Voltage Level Shifter

CD40109BE

CMOS Quad Low-to-High Voltage Lever Shifter