描述 Description

CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero. The CD40102BMS is config ured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter. Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic.

特性 Features

? High Voltage Type (20V Rating)

? CD40102BMS: 2-Decade BCD Type

? CD40103BMS: 8-Bit Binary Type

? Synchronous or Asynchronous Preset

? Medium Speed Operation

?? - fCL = 3.6MHz (Typ) at 10V

? Cascadable

? 100 Tested for Quiescent Current at 20V

? Maximum Input Current of 1μA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC

? Noise Margin (Over Full Package/Temperature Range)

?? - 1V at VDD = 5V

?? - 2V at VDD = 10V

?? - 2.5V at VDD = 15V

? Standardized Symmetrical Output Characteristics

? 5V, 10V and 15V Parametric Ratings

? Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

? Divide-By- “N” Counters

? Programmable Times

? Interrupt Timers

? Cycle/Program Counter

?