CA91數(shù)據(jù)手冊Fujitsu中文資料規(guī)格書
CA91規(guī)格書詳情
描述 Description
■ DESCRIPTION
AccelArrayTM* is a new structured ASIC family, offering short development time, and low development cost with pre-diffused IP macros into base masters and pre-designed common 3 to 4 metal layers out of 6 to 7 layers. By using 0.11 μm CMOS process technology, the devices can support 6 million logic gates, 4.55 Mbits SRAM and 3.125 Gbps high speed transmission macros. Ultra-high pin count FC-BGA (up to 729 pins to 1681 pins) packages are available.■ FEATURES
? High-speed, large scale ASIC produced in short development time:
? TAT = One third compared with Standard Cell ASICs (target value)
? Uses an architecture that simplifies physical design tasks.
? Pre-designed common masters with IR-drop free.
? Pre-designed test circuit insertion to reduce test synthesis tasks.
? Uses a dedicated timing-driven layout tool to reduce development time.
? Signal Integrity Free (pre-designed main clock trees without design verifications)
? Max built-in gate number : 6,000,000 gates or more
? Technology : 0.11 μm Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
? Internal cells support high-speed operation
? Power supply voltage : +1.2 V ± 0.1 V/2.5 V ± 0.2 V (Dual power supply. Needs 1.5 V power supply during using HTSL.).
? Operation junction temperature : ?40 °C to +125 °C (standard)
? Max operating frequency: 333 MHz (internal circuit)
? Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.)
? Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.)
? Embedded macro : PLL, SRAM
? 8-channel clock supply system incorporating a PLL
? Supports Memory-BIST/Boundary-SCAN
? Package : FC-BGA (729 pins to 1681 pins)
? ARM core is supported.
特性 Features
? High-speed, large scale ASIC produced in short development time:
? TAT = One third compared with Standard Cell ASICs (target value)
? Uses an architecture that simplifies physical design tasks.
? Pre-designed common masters with IR-drop free.
? Pre-designed test circuit insertion to reduce test synthesis tasks.
? Uses a dedicated timing-driven layout tool to reduce development time.
? Signal Integrity Free (pre-designed main clock trees without design verifications)
? Max built-in gate number : 6,000,000 gates or more
? Technology : 0.11 μm Silicon gate CMOS, 6 to 7-metal layers (wiring material: copper), low-k inter-layer film
? Internal cells support high-speed operation
? Power supply voltage : +1.2 V ± 0.1 V/2.5 V ± 0.2 V (Dual power supply. Needs 1.5 V power supply during using HTSL.).
? Operation junction temperature : ?40 °C to +125 °C (standard)
? Max operating frequency: 333 MHz (internal circuit)
? Support for fast interface/macro (200 MHz/400 MHz DDR I/F, 2.5 Gbps PCI Express, 3.125 Gbps XAUI, etc.)
? Special interfaces (P-CML,LVDS,PCI,HSTL,SSTL-2, etc.)
? Embedded macro : PLL, SRAM
? 8-channel clock supply system incorporating a PLL
? Supports Memory-BIST/Boundary-SCAN
? Package : FC-BGA (729 pins to 1681 pins)
? ARM core is supported.?
技術參數(shù)
- 型號:
CA91
- 制造商:
FUJITSU
- 制造商全稱:
Fujitsu Component Limited.
- 功能描述:
CMOS AccelArray
供應商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
---|---|---|---|---|---|---|---|
TUNDRA |
2016+ |
BGA2727 |
8880 |
只做原裝,假一罰十,公司可開17%增值稅發(fā)票! |
詢價 | ||
TUNDRA |
24+ |
BGA |
20000 |
全新原廠原裝,進口正品現(xiàn)貨,正規(guī)渠道可含稅!! |
詢價 | ||
TUNDRA |
20+ |
QFP |
500 |
樣品可出,優(yōu)勢庫存歡迎實單 |
詢價 | ||
TUNDRA |
24+ |
QFP |
90000 |
進口原裝現(xiàn)貨假一罰十價格合理 |
詢價 | ||
MOTOROLA/摩托羅拉 |
24+ |
155 |
現(xiàn)貨供應 |
詢價 | |||
TUNDRA |
23+ |
BGA |
19726 |
詢價 | |||
IDT |
24+ |
SMD |
48 |
“芯達集團”專營軍工百分之百原裝進口 |
詢價 | ||
TUNDRA |
23+ |
BGAQFP |
8659 |
原裝公司現(xiàn)貨!原裝正品價格優(yōu)勢. |
詢價 | ||
TUNDRA |
25+ |
BGA |
2650 |
原裝優(yōu)勢!絕對公司現(xiàn)貨 |
詢價 | ||
TUNDRA |
25+23+ |
QFP |
26165 |
絕對原裝正品全新進口深圳現(xiàn)貨 |
詢價 |