描述 Description

Product

特性 Features

-Produces PCI output clocks that are individually selectable for 33.3 or 66.6 MHz under SMBus or strapping control.
-Separate output buffer power supply for reduced noise, crosstalk and jitter.
-input clock frequency standard 14.31818 MHz
-Output clocks frequency individually selectable via SMBus or hardware bi-directional pin strapping.
-SSCG EMI reduction at 1.0% width
-Individual clock disables via SMBus control
-All output clocks skewed within a 500 pS window
-Cycle to Cycle jitter ±250 pS
-Output duty cycle is automatically 50% (±10%) adjusted
-Clock feed through mode and OE pins for logic testing
-Glitchless clock enabling and disabling transitions
-28-pin TSSOP or SSOP package