描述 Description

The AM275x family of highly-integrated, high-performance microcontrollers is based on the Arm Cortex R5F and C7x floating point DSP cores. The microcontrollers enable original equipment manufacturers (OEM) and original design manufacturers (ODM) to quickly bring to market devices with robust software support and rich user interfaces. The device offers the maximum flexibility of a fully integrated, mixed processor design

Key features and benefits:

Extensive audio interfacing with 5x McASP peripherals Peripherals supporting system level connectivity such as 2-port Gigabit Ethernet, USB, OSPI/QSPI, CAN-FD, UARTs, SPI and GPIOs. Supports the latest cybersecurity requirements with the built-in Hardware Security Module (HSM). One or two dual-core R5F clusters with 128KB TCM per cluster (64KB per core) and up to two C7x DSP cores with 2.25MB of L2 SRAM per C7x DSP, greatly reducing the need for external memory.

特性 Features

Dual or Quad-core Arm Cortex R5F CPU with each core running up to 1 GHz

32KB I-Cache with 64-bit ECC per CPU core

4x8KB association

Single Error Correction, Double Error Detection ECC protected per 64 bits



32KB D-cache with 64-bit ECC per CPU core

4x8KB association

Single Error Correction, Double Error Detection ECC protected per 64 bits



64KB Tightly Coupled Memory (TCM) per core, with 32-bit ECC

Single Error Correction, Double Error Detection ECC protected per 64 bits

Two Banks, A and B, 32KB each

Bank B split into B0 and B1, 16KB each



128KB TCM for CPU0 in lockstep mode



Up to 128KB Remote L2 Cache

32B cache line

Up to 128KB L2 cache covering up to 16MB cacheable space

Read only, 8-way cache

Fast Local Copy (FLC) support



For each cluster, lockstep or independent dual core operation supported



Single or Dual C7x DSP core with each core running up to 1GHz

L1 memory architecture

32KB I-Cache per core

64KB D-Cache per core



L2 memory architecture

2.25MB with ECC protection on L2 SRAM

2MB \"Main\" segment

256KB \"Auxiliary\" segment





Matrix Multiply Accelerator Version 3f (MMA3F) on DSP0



2x Asynchronous Audio Sample Rate Converter (ASRC)

140dB Signal-to-Noise ratio (SNR)

Up to 8 pairs of input and output streams (up to 16 channels total) per ASRC

Input and output sample rates from 8KHz to 216KHz

16-, 18-, 20-, 24-bit data input/output



Memory Subsystem:

Up to 6MB of On-Chip Shared SRAM

Remote Low latency L2 cache (RL2), software programmable, allocated from SRAM

432KB of On-Chip SRAM in SMS Subsystem

256KB of On-Chip RAM with SECDED ECC in SMS Subsystem

176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware





2 × Flash Sub Systems (FSS) that support Octal Serial Peripheral Interface (OSPI) at up to 166MHz SDR and 166MHz DDR at 1.8V and 3.3V with full XIP (eXecute In Place) which can be used for

1x FSS supporting OSPI OptiFlash memory technology, Firmware Over-The-Air upgrades (FOTA), and On The Fly Advanced Encryption Standard (OTFA)

1x FSS supporting OSPI or HyperRAM

RAM expansion



1 × 8-bit Multi-Media Card/Secure Digital (eMMC/SD) interface



5 × Multichannel Audio Serial Ports (McASP)

Transmit and Receive Clocks up to 50MHz

Up to 26 Serial Data Pins across 5x McASP with Independent TX and RX Clocks

Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S) and Similar Formats

Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)

FIFO Buffers for Transmit and Receive (256 Bytes)

Support for audio reference output clock



8 × Universal Asynchronous RX-TX (UART) modules

5 × Serial Peripheral Interface (SPI) controllers

8 × Inter-Integrated Circuit (I2C) ports

5 × Modular Controller Area Network (MCAN) modules with CAN-FD support

3 × Enhanced Pulse Width Modulation (ePWM) modules

6 × Enhanced Capture (ECAP) modules

1 × 12-bit Analog to Digital Converters (ADC) with 4MSPS maximum sampling rate

Up to 167 General Purpose I/O (GPIO)



Integrated Ethernet Switch supporting (total 2 external ports)

RMII (10/100) or RGMII (10/100/1000)

IEEE 1588 (Annex D, Annex E, Annex F with 802.1AS PTP)

Supports 802.1Qav (eAVB)

Clause 45 MDIO PHY management

Packet Classifier based on ALE engine with 512 classifiers

Priority flow control

Four CPU hardware interrupt pacing

IP/ UDP/ TCP checksum offload in hardware



USB 2.0

Port configurable as USB host, USB device, or USB Dual-Role device

Integrated USB VBUS detection





Hardware Security Module (HSM)

Dedicated dual-core ARM Cortex-M4F Security co-processor with dedicated interconnect for security

Dedicated security DMA and IPC subsystem for isolated processing



Secure boot support

Hardware-enforced Root-of-Trust (RoT)

Support to switch RoT via backup key

Support for takeover protection, IP protection, and anti-roll back protection



Cryptographic acceleration supported

Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream

Supports cryptographic cores

AES - 128/192/256-bit key sizes

SHA2 - 224/256/384/512-bit support

DRBG with true random number generator

PKA (Public Key Accelerator) to Assist in RSA/ECC processing: RSA-4096 bits, ECDSA, SM2DSA, Curve25519/448

Supports Chinese crypto algorithms: SM3 and SM4



DMA support



Debugging security

Secure software controlled debug access

Security aware debugging



Trusted Execution Environment (TEE) supported

Arm TrustZone based TEE

Extensive firewall support for isolation

Secure watchdog/timer/IPC



Secure storage support

On-the-Fly encryption and support for OSPI interface in XIP mode



Functional Safety-Compliant targeted [Automotive]

Developed for functional safety applications

Documentation to be made available to aid ISO 26262 functional safety system design

Systematic capability up to ASIL-D targeted

Hardware integrity up to ASIL-B targeted

Safety-related certification

ISO 26262 planned







Power modes supported by Device Manager:

Active

Standby

IO Retention





UART

I2C EEPROM

OSPI NOR/NAND Flash

SD Card

eMMC

USB (host) Mass Storage

USB (device) boot from external host (DFU mode)

Ethernet



AEC-Q100 qualified for automotive applications

16-nm FinFET technology

15.8mm x 15.8mm, 0.8mm pitch 361-pin FCCSP