ADSP-TS101SAB1-100屬于集成電路（IC）的DSP（數(shù)字信號(hào)處理器）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADSP-TS101SAB1-100DSP（數(shù)字信號(hào)處理器）數(shù)字信號(hào)處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對(duì)連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號(hào)處理等應(yīng)用。

GENERAL DESCRIPTION

The ADSP-TS101S TigerSHARC? processor is an ultrahigh performance, Static SuperscalarTM ?processor optimized for large signal processing tasks and communications infrastructure. The DSP combines very wide memory widths with dual computation blocks—supporting 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed-point processing—to set a new standard of performance for digital signal processors. The TigerSHARC processor’s Static Superscalar architecture lets the processor execute up to four instructions each cycle, performing 24 fixed-point (16-bit) operations or six floating-point operations.

FEATURES

300 MHz, 3.3 ns instruction cycle rate

6M bits of internal—on-chip—SRAM memory

19 mm × 19 mm (484-ball) or 27 mm × 27 mm

(625-ball) PBGA package

Dual computation blocks—each containing an ALU, a

multiplier, a shifter, and a register file

Dual integer ALUs, providing data addressing and pointer

manipulation

Integrated I/O includes 14-channel DMA controller, external

port, 4 link ports, SDRAM controller, programmable flag

pins, 2 timers, and timer expired pin for system integration

1149.1 IEEE compliant JTAG test access port for on-chip

emulation

On-chip arbitration for glueless multiprocessing with up to

8 TigerSHARC processors on a bus

BENEFITS

Provides high performance Static Superscalar DSP

operations, optimized for telecommunications infrastructure

and other large, demanding multiprocessor DSP

applications

Performs exceptionally well on DSP algorithm and I/O

benchmarks (see benchmarks in Table 1 and Table 2)

Supports low overhead DMA transfers between internal

memory, external memory, memory-mapped peripherals,

link ports, other DSPs (multiprocessor), and host

processors

Eases DSP programming through extremely flexible

instruction set and high-level language-friendly DSP architecture

Enables scalable multiprocessing systems with low

communications overhead