描述 Description

The ADSP-BF533 provides a high performance, power-efficient processor choice for today's most demanding convergent signal processing applications. The high performance 16-bit/32-bit Blackfin? embedded processor core, the flexible cache architecture, the enhanced DMA subsystem, and the dynamic power management (DPM) functionality allow system designers a flexible platform to address a wide range of applications including consumer,communications, automotive, and industrial/instrumentation.

Architectural FeaturesHigh performance 16-bit/32-bit embedded processor core10-stage RISC MCU/DSP pipeline with mixed 16-bit/32-bit ISA for optimal code densityFull SIMD architecture, including instructions for accelerated video and image processingMemory management unit (MMU) supporting full memory protection for an isolated and secure environment

High Level of IntegrationUp to 148 kB of on-chip SRAMGlueless video capture and display portTwo dual-channel, full-duplex, synchronous serial ports supporting eight stereo I2S channels12 DMA channels supporting one- and two-dimensional data transfersMemory controller providing glueless connection to multiple banks of external SDRAM, SRAM, Flash, or ROM160-ball mini-BGA, 169-ball PBGA packagesIndustrial temperature ranges (40°C to 85°C) and commercial temperature ranges (0°C to 70°C) available

特性 Features

? Application-tuned peripherals provide glueless connectivity to general-purpose converters in data acquisition applications



? Large on-chip SRAM for maximum system performance

簡介

ADSP-BF533屬于集成電路（IC）的DSP（數(shù)字信號處理器）。由制造生產(chǎn)的ADSP-BF533DSP（數(shù)字信號處理器）數(shù)字信號處理器是類似于微處理器或微控制器的器件，但區(qū)別在于其內(nèi)部架構(gòu)經(jīng)修改，適用于對連續(xù)數(shù)據(jù)流連續(xù)執(zhí)行以乘法和加法運(yùn)算為主的算法，而不是以條件邏輯或大量并發(fā)進(jìn)程為主的算法。該器件通常用于諸如音頻或視頻信號處理等應(yīng)用。