ADP1754屬于集成電路（IC）的穩(wěn)壓器-線性。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的ADP1754穩(wěn)壓器 - 線性線性穩(wěn)壓器用于提供穩(wěn)定的輸出電壓，無論負(fù)載電流、輸入電壓或環(huán)境因素如何變化，這些輸出電壓通常都要保持不變。它們的工作原理要求輸入電壓維持在高于所需的輸出電壓，而且要超出某個最小量，并且在工作時會將輸入端的任何多余電壓轉(zhuǎn)換為熱量。對于大多數(shù)應(yīng)用而言，雖然這種穩(wěn)壓器的效率低于開關(guān)模式的穩(wěn)壓器，但它們通常更適合對噪聲高度敏感的應(yīng)用。

FEATURES

2 A maximum output current Low input voltage supply range

VIN = 1.10 V to 1.98 V, no external bias supply required Fixed output voltage range: VOUT_FIXED = 0.9 V to 1.5 V Adjustable output voltage range: VOUT_ADJ = 0.5 V to 1.5 V Ultralow noise: 2 μV rms, 100 Hz to 100 kHz Noise spectral density

4 nV/√Hz at 10 kHz 3 nV/√Hz at 100 kHz Low dropout voltage: 62 mV typical at 2 A load Operating supply current: 4.5 mA typical at no load ±1.5% fixed output voltage accuracy over line, load, and

temperature

Excellent power supply rejection ratio (PSRR) performance

62 dB typical at 10 kHz at 2 A load

46 dB typical at 100 kHz at 2 A load Excellent load/line transient response

Soft start to reduce inrush current

Optimized for small 10 μF ceramic capacitors Current-limit and thermal overload protection

Power-good indicator

Precision enable

16-lead, 3 mm × 3 mm LFCSP package

AEC-Q100 qualified for automotive applications

APPLICATIONS

Regulation to noise sensitive applications such as radio

frequency (RF) transceivers, analog-to-digital converter

(ADC) and digital-to-analog converter (DAC) circuits,

phase-locked loops (PLLs), voltage controlled oscillators

(VCOs) and clocking integrated circuits

Field-programmable gate array (FPGA) and digital signal processor (DSP) supplies

Medical and healthcare

Industrial and instrumentation