描述 Description

The ADC12QS065 is a low power, high performance CMOS 4-channel analog-to-digital converter with LVDS serialized outputs. The ADC12QS065 digitizes signals to 12 bits resolution at sampling rates up to 65 MSPS while consuming a typical 200 mW/ADC from a single 3.3V supply. Sampled data is transformed into high speed serial LVDS output data streams. Clock and frame LVDS pairs aid in data capture. The ADC12QS065’s six differential pairs transmit data over backplanes or cable and also make PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. No missing codes performance is ensured over the full operating temperature range. The pipeline ADC architecture achieves 11 Effective Bits over the entire Nyquist band at 65 MSPS.When not converting, power consumption can be reduced by pulling the PD (Power Down) pin high, placing the converter into a low power state where it typically consumes less than 3 mW total, and from which recovery is less than 5 ms. The ADC12QS065's speed, resolution and single supply operation makes it well suited for a variety of applications in ultrasound, imaging, video and communications. Operating over the industrial (-40°C to +85°C) temperature range, the ADC12QS065 is available in a 60-pin WQFN package with exposed pad (9x9x0.8mm, 0.5mm pin pitch).

特性 Features

? Single +3.3V Supply Operation
? Internal Sample-and-Hold and Internal Reference
? Low Power Consumption
? Power Down Mode
? Clock and Data Frame Timing
? 780 Mbps Serial LVDS Data Rate (at 65 MHz Clock)
? LVDS Serial Output Rated for 100 Ohm Load
Key Specifications
? Resolution: 12 Bits
? DNL: ±0.3 LSB (Typ)
? SNR (fIN = 5 MHz): 69 dB (Typ)
? SFDR (fIN = 5 MHz): 83 dB (Typ)
? ENOB (at Nyquist): 11 Bits (Typ)
? Power Consumption
? Operating, 65 MSPS, per ADC: 200 mW (Typ)
? Power Down Mode: