1FEATURES

2? Choice of Binary or 2’s Complement Output

Format

? Single +3.3V Supply Operation

? Outputs 2.4V to 3.3V Compatible

? Pin Compatible with ADC12D040

? Power Down Mode

? Internal/External Reference

KEY SPECIFICATIONS

? Resolution: 12 Bits

? DNL: ±0.5 LSB (typ)

? SNR (fIN = 10 MHz): 66 dB (typ)

? SFDR (fIN = 10 MHz): 81 dB (typ)

? Power Consumption

– Operating: 686 mW (typ)

– Power Down Mode: 75 mW (typ)

APPLICATIONS

? Ultrasound and Imaging

? Instrumentation

? Communications Receivers

? Sonar/Radar

? xDSL

? Cable Modems

? DSP Front Ends

DESCRIPTION

The ADC12DL066 is a dual, low power monolithic

CMOS analog-to-digital converter capable of

converting analog input signals into 12-bit digital

words at 66 Megasamples per second (Msps),

minimum. This converter uses a differential, pipeline

architecture with digital error correction and an onchip

sample-and-hold circuit to minimize die size and

power consumption while providing excellent dynamic

performance and a 450 MHz Full Power Bandwidth.

Operating on a single 3.3V power supply, the

ADC12DL066 achieves 10.7 effective bits and

consumes just 686 mW at 66 Msps, including the

reference current. The Power Down feature reduces

power consumption to 75 mW.

The differential inputs provide a full scale differential

input swing equal to 2 times VREF with the possibility

of a single-ended input. Full use of the differential

input is recommended for optimum performance. The

digital outputs from the two ADCs are available on

separate 12-bit buses with an output data format

choice of offset binary or two’s complement.

To ease interfacing to lower voltage systems, the

digital output driver power pins of the ADC12DL066

can be connected to a separate supply voltage in the

range of 2.4V to the digital supply voltage.

This device is available in the 64-lead TQFP package

and will operate over the industrial temperature range

of ?40°C to +85°C. An evaluation board is available

to ease the evaluation process.