AD9744ACPZRL7屬于集成電路（IC）的數(shù)模轉(zhuǎn)換器（DAC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9744ACPZRL7數(shù)模轉(zhuǎn)換器（DAC）數(shù)模轉(zhuǎn)換器（DAC、D/A、D2A 或 D 轉(zhuǎn) A）可將數(shù)字信號轉(zhuǎn)換為緩沖或無緩沖的模擬電壓或電流。DAC 架構(gòu)是否適合特定應(yīng)用，要取決于分辨率和采樣頻率。DAC 通常用于音樂播放器，將數(shù)字?jǐn)?shù)據(jù)流轉(zhuǎn)換為模擬音頻流。它們還用于電視和手機，將數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換為模擬視頻信號，再連接到屏幕驅(qū)動器，以顯示單色或彩色圖像。

GENERAL DESCRIPTION

The AD97441 is a 14-bit resolution, wideband, third generation

member of the TxDAC series of high performance, low power

CMOS digital-to-analog converters (DACs). The TxDAC family,

consisting of pin-compatible 8-, 10-, 12-, and 14-bit DACs, is

specifically optimized for the transmit signal path of communication

systems. All of the devices share the same interface options,

small outline package, and pinout, providing an upward or

downward component selection path based on performance,

resolution, and cost. The AD9744 offers exceptional ac and dc

performance while supporting update rates up to 210 MSPS.

The AD9744’s low power dissipation makes it well suited for

portable and low power applications. Its power dissipation can

be further reduced to a mere 60 mW with a slight degradation

in performance by lowering the full-scale current output. Also,

a power-down mode reduces the standby power dissipation to

approximately 15 mW. A segmented current source architecture

is combined with a proprietary switching technique to reduce

spurious components and enhance dynamic performance.

Edge-triggered input latches and a 1.2 V temperature compensated

band gap reference have been integrated to provide a complete

monolithic DAC solution. The digital inputs support 3 V

CMOS logic families.

FEATURES

High performance member of pin-compatible

TxDAC product family

Excellent spurious-free dynamic range performance

SFDR to Nyquist

83 dBc at 5 MHz output

80 dBc at 10 MHz output

73 dBc at 20 MHz output

SNR at 5 MHz output, 125 MSPS: 77 dB

Twos complement or straight binary data format

Differential current outputs: 2 mA to 20 mA

Power dissipation: 135 mW at 3.3 V

Power-down mode: 15 mW at 3.3 V

On-chip 1.2 V reference

CMOS-compatible digital interface

28-lead SOIC, 28-lead TSSOP, and 32-lead LFCSP packages

Edge-triggered latches

APPLICATIONS

Wideband communication transmit channel

Direct IFs

Base stations

Wireless local loops

Digital radio links

Direct digital synthesis (DDS)

Instrumentation