AD9650BCPZRL7-65屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導體技術(shù)有限公司制造生產(chǎn)的AD9650BCPZRL7-65模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9650 is a dual, 16-bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS analog-to-digital converter (ADC) designed for digitizing high frequency, wide dynamic range signals with input frequencies of up to 300 MHz. The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers, and shared integrated voltage reference, which eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

FEATURES

1.8 V analog supply operation

1.8 V CMOS or LVDS output supply

SNR

82 dBFS at 30 MHz input and 105 MSPS data rate

83 dBFS at 9.7 MHz input and 25 MSPS data rate

SFDR

90 dBc at 30 MHz input and 105 MSPS data rate

95 dBc at 9.7 MHz input and 25 MSPS data rate

Low power

328 mW per channel at 105 MSPS

119 mW per channel at 25 MSPS

Integer 1-to-8 input clock divider

IF sampling frequencies to 300 MHz

Analog input range of 2.7 V p-p

Optional on-chip dither

Integrated ADC sample-and-hold inputs

Differential analog inputs with 500 MHz bandwidth

ADC clock duty cycle stabilizer

APPLICATIONS

Industrial instrumentation

X-Ray, MRI, and ultrasound equipment

High speed pulse acquisition

Chemical and spectrum analysis

Direct conversion receivers

Multimode digital receivers

Smart antenna systems

General-purpose software radios