AD9608BCPZRL7-105屬于集成電路（IC）的模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9608BCPZRL7-105模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器（ADC、A/D 或 A 轉(zhuǎn) D）對模擬信號進行采樣，例如由麥克風(fēng)采集的聲音或傳感器的輸出，然后將其轉(zhuǎn)換為數(shù)字信號。一般來說，數(shù)字輸出是二進制補碼二進制數(shù)，與輸入成比例。輸入類型可能是差分、偽差分或單端輸入。模數(shù)轉(zhuǎn)換器可按照位數(shù)、采樣率、輸入數(shù)、接口、轉(zhuǎn)換器數(shù)和架構(gòu)（例如自適應(yīng)增量、雙斜率、折疊、流水線、SAR、三角積分、兩步式）進行選擇。

GENERAL DESCRIPTION

The AD9608 is a monolithic, dual-channel, 1.8 V supply, 10-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC) that features a high performance sample-and-hold circuit and an on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 10-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.

FEATURES

1.8 V analog supply operation

1.8 V CMOS or 1.8 V LVDS output

SNR = 61.7 dBFS at 70 MHz

SFDR = 85 dBc at 70 MHz

Low power: 71 mW/channel ADC core at 125 MSPS

Differential analog input with 650 MHz bandwidth

IF sampling frequencies to 200 MHz

On-chip voltage reference and sample-and-hold circuit

2 V p-p differential analog input

DNL = ±0.13 LSB

Serial port control options

Offset binary, Gray code, or twos complement data format

Optional clock duty cycle stabilizer

Integer 1-to-8 input clock divider

Data output multiplex option

Built-in selectable digital test pattern generation

Energy-saving power-down modes

Data clock out with programmable clock and data alignment