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AD9572

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572

光纖通道/以太網(wǎng)時鐘發(fā)生器IC，PLL內(nèi)核，分頻器，7路時鐘輸出; ? 完全集成的雙VCO/PLL內(nèi)核\n均方根抖動：167 fs（0.637 MHz至10 MHz，\n 106.25 MHz）\n均方根抖動：178 fs（1.875 MHz至20 MHz，\n 156.25 MHz） \n\n? 均方根抖動：418 fs（12 kHz至20 MHz，\n125 MHz輸入晶振或25 MHz時鐘頻率）\n\n? 針對106.25 MHz、156.25 MHz、33.33 MHz、100 MHz、125 MHz提供預(yù)設(shè)分頻比\n\n? 可選擇LVPECL或LVDS輸出格式\n\n? 集成環(huán)路濾波器\n\n\n\n? 參考時鐘輸出副本\n\n? 通過綁定引腳配置速率\n\n? 節(jié)省空間的6 mm × 6 mm、40引腳LFCSP封裝\n\n? 功耗：0.71 W（LVDS工作方式）\n\n? 功耗：1.07 W（LVPECL工作方式）\n\n? 3.3 V 工作電壓;

AD9572是一款多輸出時鐘發(fā)生器，具有兩個片內(nèi)PLL內(nèi)核，針對包括以太網(wǎng)接口的光纖通道線路卡應(yīng)用進行了優(yōu)化。整數(shù)N分頻PLL設(shè)計基于ADI公司成熟的高性能、低抖動頻率合成器系列，可實現(xiàn)網(wǎng)絡(luò)的較高性能。這款器件也適合相位噪聲和抖動要求嚴(yán)格的其它應(yīng)用。 PLL部分由低噪聲鑒頻鑒相器(PFD)、精密電荷泵(CP)、低相位噪聲壓控振蕩器(VCO)、預(yù)編程的反饋分頻器和輸出分頻器組成。通過將一個外部晶振或參考時鐘連接到REFCLK引腳，可以將最高156.25 MHz的頻率鎖定至輸入?yún)⒖?。每個輸出分頻比和反饋分頻比針對所要求的輸出速率進行預(yù)編程。 \n\n 第二個PLL也用作整數(shù)N分頻頻率合成器，并驅(qū)動兩個LVPECL或LVDS輸出緩沖器以支持106.25 MHz頻率。無需外部環(huán)路濾波器，從而節(jié)省寶貴的設(shè)計時間和電路板空間。 \n\n AD9572提供40引腳6 mm × 6 mm、LFCSP封裝，可以采用3.3 V單電源供電。溫度范圍為?40°C至+85°C。\n\n

AD9572ACPZLVD

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572ACPZLVD-R7

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572ACPZLVD-RL

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572ACPZPEC

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572ACPZPEC-R7

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572ACPZPEC-RL

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572-EVALZ-LVD

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman

AD9572-EVALZ-PEC

Fiber Channel/Ethernet Clock Generator IC, PLL Core, Dividers, 7 Clock Outputs

GENERALDESCRIPTION TheAD9572providesamultioutputclockgeneratorfunctionalongwithtwoon-chipPLLcores,optimizedforfiberchannellinecardapplicationsthatincludeanEthernetinterface.Theinteger-NPLLdesignisbasedontheAnalogDevices,Inc.,provenportfolioofhighperforman