AD9547BCPZ-REEL7屬于集成電路（IC）的應(yīng)用特定時(shí)鐘/定時(shí)。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9547BCPZ-REEL7應(yīng)用特定時(shí)鐘/定時(shí)專用時(shí)鐘和計(jì)時(shí) IC（集成電路）產(chǎn)品族中的產(chǎn)品主要用于執(zhí)行與時(shí)間或頻率信息生成和分配相關(guān)的各種操作，適合的設(shè)計(jì)環(huán)境較特定，例如 AMD 和 Intel 的中央處理單元 (CPU) 或圖形處理單元 (GPU)、DVD 音頻設(shè)備、藍(lán)光光盤播放器、以太網(wǎng)設(shè)備、PCIe、SATA、光纖通道接口、車載娛樂總線等。

GENERAL DESCRIPTION

The AD9547 provides synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9547 generates an output clock that is synchronized to one of two differential or four single-ended external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The AD9547 continuously generates a clean (low jitter), valid output clock, even when all references fail, by means of digitally controlled loop and holdover circuitry.

The AD9547 operates over an industrial temperature range of ?40°C to +85°C.

FEATURES

Supports Stratum 2 stability in holdover mode

Supports reference switchover with phase build-out

Supports hitless reference switchover

Automatic/manual holdover and reference switchover

2 pairs of reference input pins, with each pair configurable

as a single differential input or as 2 independent single-ended inputs

Input reference frequencies from 1 kHz to 750 MHz

Reference validation and frequency monitoring (1 ppm)

Programmable input reference switchover priority

30-bit programmable input reference divider

2 pairs of clock output pins, with each pair configurable as

a single differential LVDS/LVPECL output or as 2 single-ended CMOS outputs

Output frequencies up to 450 MHz

20-bit integer and 10-bit fractional programmable feedback

divider

Programmable digital loop filter covering loop bandwidths

from 0.001 Hz to 100 kHz

Optional low noise LC-VCO system clock multiplier

Optional crystal resonator for system clock input

On-chip EEPROM to store multiple power-up profiles

Software controlled power-down

64-lead LFCSP package

APPLICATIONS

Network synchronization

Cleanup of reference clock jitter

SONET/SDH clocks up to OC-192, including FEC

Stratum 2 holdover, jitter cleanup, and phase transient

control

Stratum 3E and Stratum 3 reference clocks

Wireless base stations, controllers

Cable infrastructure

Data communications