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AD9520-2SLASHPCBZ中文資料亞德諾數據手冊PDF規(guī)格書

AD9520-2SLASHPCBZ
廠商型號

AD9520-2SLASHPCBZ

功能描述

12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO

文件大小

1.64165 Mbytes

頁面數量

84

生產廠商 Analog Devices
企業(yè)簡稱

AD亞德諾

中文名稱

亞德諾半導體技術有限公司官網

原廠標識
數據手冊

下載地址一下載地址二到原廠下載

更新時間

2025-7-20 1:06:00

人工找貨

AD9520-2SLASHPCBZ價格和庫存,歡迎聯(lián)系客服免費人工找貨

AD9520-2SLASHPCBZ規(guī)格書詳情

GENERAL DESCRIPTION

The AD9520-21 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.02 GHz to 2.335 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.

The AD9520 serial interface supports both SPI and I2C? ports. An in-package EEPROM can be programmed through the serial interface and store user-defined register settings for power-up and chip reset.

The AD9520 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs.

FEATURES

Low phase noise, phase-locked loop (PLL)

On-chip VCO tunes from 2.02 GHz to 2.335 GHz

Supports external 3.3 V/5 V VCO/VCXO to 2.4 GHz

1 differential or 2 single-ended reference inputs

Accepts CMOS, LVDS, or LVPECL references to 250 MHz

Accepts 16.67 MHz to 33.3 MHz crystal for reference input

Optional reference clock doubler

Reference monitoring capability

Auto and manual reference switchover/holdover modes, with selectable revertive/nonrevertive switching

Glitch-free switchover between references

Automatic recovery from holdover

Digital or analog lock detect, selectable

Optional zero delay operation

Twelve 1.6 GHz LVPECL outputs divided into 4 groups

Each group of 3 has a 1-to-32 divider with phase delay

Additive output jitter as low as 225 fs rms

Channel-to-channel skew grouped outputs <16 ps

Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)

Automatic synchronization of all outputs on power-up

Manual synchronization of outputs as needed

SPI- and I2C-compatible serial control port

64-lead LFCSP

Nonvolatile EEPROM stores configuration settings

APPLICATIONS

Low jitter, low phase noise clock distribution

Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols

Forward error correction (G.710)

Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

High performance wireless transceivers

ATE and high performance instrumentation

Broadband infrastructures

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