AD9434-370EBZ屬于開(kāi)發(fā)板套件編程器的評(píng)估板-模數(shù)轉(zhuǎn)換器（ADC）。由亞德諾半導(dǎo)體技術(shù)有限公司制造生產(chǎn)的AD9434-370EBZ評(píng)估板 - 模數(shù)轉(zhuǎn)換器（ADC）模數(shù)轉(zhuǎn)換器 (ADC) 評(píng)估板是預(yù)裝有元器件的電路板，用于提供特定 ADC 或器件工作實(shí)例。特定板上的 A/D 轉(zhuǎn)換器數(shù)量從 3 到 32 不等，每秒采樣率從 2.5 kHz 到 26 GHz 不等，輸入電壓范圍從 0 到 8 Vp-p。

GENERAL DESCRIPTION

The AD9434is a 12-bit monolithic sampling analog-to-digital converter (ADC) optimized for high performance, low power, and ease of use. The part operates at up to a 500 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution. The VREF pin can be used to monitor the internal reference or provide an external voltage reference (external reference mode must be enabled through the SPI port).

FEATURES

SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS

ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (?1.0 dBFS)

SFDR = 78 dBc at fIN up to 250 MHz at 500 MSPS (?1.0 dBFS)

Integrated input buffer

Excellent linearity

DNL = ±0.5 LSB typical

INL = ±0.6 LSB typical

LVDS at 500 MSPS (ANSI-644 levels)

1 GHz full power analog bandwidth

On-chip reference, no external decoupling required

Low power dissipation

690 mW at 500 MSPS—LVDS SDR mode

660 mW at 500 MSPS—LVDS DDR mode

Programmable (nominal) input voltage range

1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal

1.8 V analog and digital supply operation

Selectable output data format (offset binary, twos

complement, Gray code)

Clock duty cycle stabilizer

Integrated data clock output with programmable clock and

data alignment

APPLICATIONS

Wireless and wired broadband communications

Cable reverse path

Communications test equipment

Radar and satellite subsystems

Power amplifier linearization